| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.67 | 99.33 | 99.04 | 100.00 | 100.00 | 100.00 | 99.66 |
| T504 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3420388507 | Oct 03 08:56:41 AM UTC 24 | Oct 03 08:56:43 AM UTC 24 | 20989837 ps | ||
| T505 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1424164088 | Oct 03 08:56:41 AM UTC 24 | Oct 03 08:56:43 AM UTC 24 | 62909926 ps | ||
| T506 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.210881711 | Oct 03 08:56:41 AM UTC 24 | Oct 03 08:56:43 AM UTC 24 | 19460494 ps | ||
| T507 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3837116487 | Oct 03 08:56:40 AM UTC 24 | Oct 03 08:56:43 AM UTC 24 | 58114900 ps | ||
| T508 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.1070018932 | Oct 03 08:56:40 AM UTC 24 | Oct 03 08:56:43 AM UTC 24 | 175527396 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1466346173 | Oct 03 08:56:41 AM UTC 24 | Oct 03 08:56:43 AM UTC 24 | 114710515 ps | ||
| T509 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.3058671464 | Oct 03 08:56:40 AM UTC 24 | Oct 03 08:56:43 AM UTC 24 | 289304103 ps | ||
| T510 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.3643244630 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:44 AM UTC 24 | 35019886 ps | ||
| T511 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.1476560464 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:44 AM UTC 24 | 15601891 ps | ||
| T512 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.259439555 | Oct 03 08:56:48 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 13717776 ps | ||
| T513 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.465949914 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:44 AM UTC 24 | 33865815 ps | ||
| T514 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.3563586323 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 13610346 ps | ||
| T515 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.300941663 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:44 AM UTC 24 | 74068482 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1852889974 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:44 AM UTC 24 | 89243133 ps | ||
| T516 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3845712266 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:44 AM UTC 24 | 22625677 ps | ||
| T517 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.373827402 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:44 AM UTC 24 | 22546797 ps | ||
| T518 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.791961092 | Oct 03 08:56:41 AM UTC 24 | Oct 03 08:56:44 AM UTC 24 | 133708770 ps | ||
| T519 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1725694536 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:44 AM UTC 24 | 55082431 ps | ||
| T520 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2358011145 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:44 AM UTC 24 | 476517350 ps | ||
| T521 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2332099699 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:44 AM UTC 24 | 389688666 ps | ||
| T522 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.3977939925 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:45 AM UTC 24 | 123554916 ps | ||
| T523 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.1275161865 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 25443481 ps | ||
| T524 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.1809446680 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:45 AM UTC 24 | 31241357 ps | ||
| T525 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.4154988565 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:45 AM UTC 24 | 33570882 ps | ||
| T526 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.4232787410 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 13877458 ps | ||
| T527 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1896382680 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:45 AM UTC 24 | 63595778 ps | ||
| T528 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.2104931752 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 27409987 ps | ||
| T529 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4165129040 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:45 AM UTC 24 | 23679173 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.2422922903 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:45 AM UTC 24 | 42082529 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1835739558 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:45 AM UTC 24 | 13701336 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.2603123909 | Oct 03 08:56:42 AM UTC 24 | Oct 03 08:56:45 AM UTC 24 | 590475564 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2931989140 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:45 AM UTC 24 | 31978449 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.2373899012 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:45 AM UTC 24 | 22351107 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.1420370684 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:46 AM UTC 24 | 19919533 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1557300477 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:46 AM UTC 24 | 80836013 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.724186749 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:46 AM UTC 24 | 114427662 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2510752425 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:46 AM UTC 24 | 35110986 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3036833433 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:46 AM UTC 24 | 131740081 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4242197049 | Oct 03 08:56:43 AM UTC 24 | Oct 03 08:56:46 AM UTC 24 | 411895122 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.2435305631 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:46 AM UTC 24 | 107440414 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.455762156 | Oct 03 08:56:43 AM UTC 24 | Oct 03 08:56:46 AM UTC 24 | 77003077 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2485786179 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:46 AM UTC 24 | 258912201 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.2307380380 | Oct 03 08:56:44 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 75719462 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.226314542 | Oct 03 08:56:45 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 36350463 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.373897094 | Oct 03 08:56:45 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 12748568 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.4280254553 | Oct 03 08:56:45 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 27934272 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.898507706 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 19149405 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1486755664 | Oct 03 08:56:45 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 19262526 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.744097260 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 53093433 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.839788326 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 22451411 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.3308458519 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 40551956 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3643391049 | Oct 03 08:56:45 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 170957973 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2799732503 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 38815652 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.4268854198 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 111599083 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.2803350635 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 176373537 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.623180221 | Oct 03 08:56:45 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 60305954 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.3078112913 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 83994515 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.46357447 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 70768125 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.1235059000 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 11010102 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.4077318040 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 30639032 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2680091276 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 18685929 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1883289086 | Oct 03 08:56:46 AM UTC 24 | Oct 03 08:56:47 AM UTC 24 | 16204049 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.579751 | Oct 03 08:56:45 AM UTC 24 | Oct 03 08:56:48 AM UTC 24 | 136488570 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.2774022174 | Oct 03 08:56:45 AM UTC 24 | Oct 03 08:56:48 AM UTC 24 | 284632793 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.1264988587 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 23458745 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.650603051 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 11952759 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.767195228 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 15913229 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.1134070526 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 40395781 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.2853938469 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 31588699 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2181536843 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 34940793 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.2945946548 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 21088820 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.3415179602 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 25216525 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.181175035 | Oct 03 08:56:47 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 14265948 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.4035404853 | Oct 03 08:56:48 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 42345186 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.2851850534 | Oct 03 08:56:48 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 28304278 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.2185610163 | Oct 03 08:56:48 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 51703494 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.4055925168 | Oct 03 08:56:48 AM UTC 24 | Oct 03 08:56:49 AM UTC 24 | 64328161 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.192490119 | Oct 03 08:56:49 AM UTC 24 | Oct 03 08:56:50 AM UTC 24 | 15594920 ps | ||
| T579 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.3496565400 | Oct 03 08:56:49 AM UTC 24 | Oct 03 08:56:50 AM UTC 24 | 46130969 ps | ||
| T580 | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.883680590 | Oct 03 08:56:49 AM UTC 24 | Oct 03 08:56:50 AM UTC 24 | 13019154 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.534787336 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 168218710325 ps |
| CPU time | 176.44 seconds |
| Started | Oct 03 08:58:20 AM UTC 24 |
| Finished | Oct 03 09:01:20 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534787336 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.534787336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all_with_rand_reset.3846834431 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2208327884 ps |
| CPU time | 21.45 seconds |
| Started | Oct 03 09:09:24 AM UTC 24 |
| Finished | Oct 03 09:09:47 AM UTC 24 |
| Peak memory | 203184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3846834431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.rv_timer_stress_all_with_rand_reset.3846834431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2059518506 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 51289497 ps |
| CPU time | 0.84 seconds |
| Started | Oct 03 08:56:24 AM UTC 24 |
| Finished | Oct 03 08:56:26 AM UTC 24 |
| Peak memory | 199956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059518506 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.2059518506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.2875969215 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3105146428861 ps |
| CPU time | 4297.37 seconds |
| Started | Oct 03 09:06:35 AM UTC 24 |
| Finished | Oct 03 10:19:06 AM UTC 24 |
| Peak memory | 202640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875969215 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.2875969215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.301561005 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 839540862465 ps |
| CPU time | 1344.39 seconds |
| Started | Oct 03 09:38:17 AM UTC 24 |
| Finished | Oct 03 10:00:56 AM UTC 24 |
| Peak memory | 203024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301561005 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.301561005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/25.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.665682708 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 461530476154 ps |
| CPU time | 550.21 seconds |
| Started | Oct 03 08:57:14 AM UTC 24 |
| Finished | Oct 03 09:06:34 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665682708 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.665682708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.3562149613 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 377533842949 ps |
| CPU time | 1224.38 seconds |
| Started | Oct 03 09:34:06 AM UTC 24 |
| Finished | Oct 03 09:54:45 AM UTC 24 |
| Peak memory | 202768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562149613 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.3562149613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/11.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.3797413344 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 683523714343 ps |
| CPU time | 1781.8 seconds |
| Started | Oct 03 09:35:38 AM UTC 24 |
| Finished | Oct 03 10:05:39 AM UTC 24 |
| Peak memory | 202636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797413344 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.3797413344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/20.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.1016795685 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2178292831975 ps |
| CPU time | 1097.24 seconds |
| Started | Oct 03 09:37:52 AM UTC 24 |
| Finished | Oct 03 09:56:22 AM UTC 24 |
| Peak memory | 202636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016795685 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.1016795685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/24.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.2246087196 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 3528485467653 ps |
| CPU time | 2461.12 seconds |
| Started | Oct 03 09:39:29 AM UTC 24 |
| Finished | Oct 03 10:20:56 AM UTC 24 |
| Peak memory | 202708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246087196 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.2246087196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/27.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1665587412 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 18854539 ps |
| CPU time | 0.74 seconds |
| Started | Oct 03 08:56:26 AM UTC 24 |
| Finished | Oct 03 08:56:28 AM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665587412 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.1665587412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.2503167346 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 397256882286 ps |
| CPU time | 798.15 seconds |
| Started | Oct 03 09:41:04 AM UTC 24 |
| Finished | Oct 03 09:54:31 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503167346 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.2503167346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/30.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.3106052704 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 627289951608 ps |
| CPU time | 2481.54 seconds |
| Started | Oct 03 09:48:09 AM UTC 24 |
| Finished | Oct 03 10:29:58 AM UTC 24 |
| Peak memory | 202768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106052704 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.3106052704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/42.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.1726806481 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 527706692741 ps |
| CPU time | 820.76 seconds |
| Started | Oct 03 09:36:58 AM UTC 24 |
| Finished | Oct 03 09:50:49 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726806481 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.1726806481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/22.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.222975941 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1012739619401 ps |
| CPU time | 3022.12 seconds |
| Started | Oct 03 09:34:02 AM UTC 24 |
| Finished | Oct 03 10:24:57 AM UTC 24 |
| Peak memory | 202880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222975941 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.222975941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/8.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.663115708 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 277226516031 ps |
| CPU time | 1506.32 seconds |
| Started | Oct 03 09:39:08 AM UTC 24 |
| Finished | Oct 03 10:04:31 AM UTC 24 |
| Peak memory | 202900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663115708 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.663115708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/26.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.995780299 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 666183711 ps |
| CPU time | 0.99 seconds |
| Started | Oct 03 08:58:17 AM UTC 24 |
| Finished | Oct 03 08:58:19 AM UTC 24 |
| Peak memory | 232592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995780299 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.995780299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.4279155083 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 469736360373 ps |
| CPU time | 1359.49 seconds |
| Started | Oct 03 09:35:10 AM UTC 24 |
| Finished | Oct 03 09:58:05 AM UTC 24 |
| Peak memory | 202636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279155083 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.4279155083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/19.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.1211452147 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1053819527632 ps |
| CPU time | 1206.4 seconds |
| Started | Oct 03 09:34:21 AM UTC 24 |
| Finished | Oct 03 09:54:42 AM UTC 24 |
| Peak memory | 202488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211452147 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.1211452147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/17.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.2089710448 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3453136863465 ps |
| CPU time | 1322.68 seconds |
| Started | Oct 03 09:28:23 AM UTC 24 |
| Finished | Oct 03 09:50:43 AM UTC 24 |
| Peak memory | 202632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089710448 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.2089710448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.3684662672 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 522616931146 ps |
| CPU time | 1321.01 seconds |
| Started | Oct 03 09:46:11 AM UTC 24 |
| Finished | Oct 03 10:08:27 AM UTC 24 |
| Peak memory | 202900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684662672 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.3684662672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/39.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.3514730043 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 546245582762 ps |
| CPU time | 2561.03 seconds |
| Started | Oct 03 09:34:04 AM UTC 24 |
| Finished | Oct 03 10:17:14 AM UTC 24 |
| Peak memory | 202440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514730043 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.3514730043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/9.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.1909343316 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 588156209960 ps |
| CPU time | 2346.71 seconds |
| Started | Oct 03 09:46:48 AM UTC 24 |
| Finished | Oct 03 10:26:19 AM UTC 24 |
| Peak memory | 202636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909343316 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.1909343316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/40.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.3633902741 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 203570918116 ps |
| CPU time | 575.5 seconds |
| Started | Oct 03 09:29:26 AM UTC 24 |
| Finished | Oct 03 09:39:11 AM UTC 24 |
| Peak memory | 202960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633902741 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3633902741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/8.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.23105994 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 455838571378 ps |
| CPU time | 759.8 seconds |
| Started | Oct 03 09:56:00 AM UTC 24 |
| Finished | Oct 03 10:08:49 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23105994 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.23105994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/68.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.622480473 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 857835861923 ps |
| CPU time | 2489.81 seconds |
| Started | Oct 03 09:34:10 AM UTC 24 |
| Finished | Oct 03 10:16:08 AM UTC 24 |
| Peak memory | 202608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622480473 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.622480473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/13.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.3936631652 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 114932899336 ps |
| CPU time | 406.42 seconds |
| Started | Oct 03 09:04:11 AM UTC 24 |
| Finished | Oct 03 09:11:04 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936631652 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3936631652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.1931145477 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1146108387787 ps |
| CPU time | 1592.61 seconds |
| Started | Oct 03 09:44:55 AM UTC 24 |
| Finished | Oct 03 10:11:47 AM UTC 24 |
| Peak memory | 202832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931145477 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.1931145477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/37.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.1637431761 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 352691799565 ps |
| CPU time | 864.99 seconds |
| Started | Oct 03 09:34:12 AM UTC 24 |
| Finished | Oct 03 09:48:48 AM UTC 24 |
| Peak memory | 202636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637431761 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.1637431761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/14.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.2890692260 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 150550717749 ps |
| CPU time | 2630.34 seconds |
| Started | Oct 03 10:08:50 AM UTC 24 |
| Finished | Oct 03 10:53:10 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890692260 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2890692260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/145.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.1259261622 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 79081220012 ps |
| CPU time | 193.95 seconds |
| Started | Oct 03 10:15:49 AM UTC 24 |
| Finished | Oct 03 10:19:06 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259261622 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1259261622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/192.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.2097148009 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 610998293984 ps |
| CPU time | 1777.12 seconds |
| Started | Oct 03 09:40:22 AM UTC 24 |
| Finished | Oct 03 10:10:19 AM UTC 24 |
| Peak memory | 202960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097148009 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2097148009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/29.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.2420119953 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 123664007674 ps |
| CPU time | 802.3 seconds |
| Started | Oct 03 10:02:33 AM UTC 24 |
| Finished | Oct 03 10:16:05 AM UTC 24 |
| Peak memory | 202900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420119953 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2420119953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/103.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.2922663451 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 340149821823 ps |
| CPU time | 538.68 seconds |
| Started | Oct 03 10:03:03 AM UTC 24 |
| Finished | Oct 03 10:12:08 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922663451 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2922663451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/108.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.4238338627 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2461293952854 ps |
| CPU time | 2348.94 seconds |
| Started | Oct 03 09:34:08 AM UTC 24 |
| Finished | Oct 03 10:13:44 AM UTC 24 |
| Peak memory | 202324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238338627 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.4238338627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.2838735105 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 170276715905 ps |
| CPU time | 3324.03 seconds |
| Started | Oct 03 10:08:09 AM UTC 24 |
| Finished | Oct 03 11:04:13 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838735105 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2838735105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/142.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.1071631987 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 287087542232 ps |
| CPU time | 912.75 seconds |
| Started | Oct 03 10:13:03 AM UTC 24 |
| Finished | Oct 03 10:28:27 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071631987 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1071631987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/173.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.2872754054 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 473942394193 ps |
| CPU time | 1406.87 seconds |
| Started | Oct 03 10:15:53 AM UTC 24 |
| Finished | Oct 03 10:39:38 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872754054 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2872754054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/195.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.2078327358 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 159207110966 ps |
| CPU time | 2338.83 seconds |
| Started | Oct 03 09:02:47 AM UTC 24 |
| Finished | Oct 03 09:42:18 AM UTC 24 |
| Peak memory | 202700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078327358 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2078327358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.2980529051 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2335507585669 ps |
| CPU time | 782.07 seconds |
| Started | Oct 03 09:14:25 AM UTC 24 |
| Finished | Oct 03 09:27:39 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980529051 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2980529051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/6.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.2211504803 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 706687162544 ps |
| CPU time | 3934.47 seconds |
| Started | Oct 03 09:02:25 AM UTC 24 |
| Finished | Oct 03 10:08:49 AM UTC 24 |
| Peak memory | 203028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211504803 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.2211504803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.442279833 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 240293750968 ps |
| CPU time | 675.13 seconds |
| Started | Oct 03 10:03:47 AM UTC 24 |
| Finished | Oct 03 10:15:10 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442279833 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.442279833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/110.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.987488817 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 524488499198 ps |
| CPU time | 538.66 seconds |
| Started | Oct 03 10:05:39 AM UTC 24 |
| Finished | Oct 03 10:14:45 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987488817 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.987488817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/123.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.3648844137 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 160482485412 ps |
| CPU time | 313.19 seconds |
| Started | Oct 03 10:12:01 AM UTC 24 |
| Finished | Oct 03 10:17:19 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648844137 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3648844137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/165.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.3664862585 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 244498223339 ps |
| CPU time | 844.89 seconds |
| Started | Oct 03 10:13:16 AM UTC 24 |
| Finished | Oct 03 10:27:31 AM UTC 24 |
| Peak memory | 201100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664862585 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3664862585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/174.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.4058272396 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1495307518678 ps |
| CPU time | 964.15 seconds |
| Started | Oct 03 09:34:30 AM UTC 24 |
| Finished | Oct 03 09:50:46 AM UTC 24 |
| Peak memory | 202636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058272396 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.4058272396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/18.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.1065265512 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 257601348591 ps |
| CPU time | 907.07 seconds |
| Started | Oct 03 09:57:59 AM UTC 24 |
| Finished | Oct 03 10:13:17 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065265512 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1065265512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/78.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.2545597494 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 69092683021 ps |
| CPU time | 184.11 seconds |
| Started | Oct 03 09:32:30 AM UTC 24 |
| Finished | Oct 03 09:35:38 AM UTC 24 |
| Peak memory | 200984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545597494 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.2545597494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3726878880 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 101288544 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:40 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726878880 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.3726878880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.1939538197 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 114976021060 ps |
| CPU time | 1432.6 seconds |
| Started | Oct 03 10:02:11 AM UTC 24 |
| Finished | Oct 03 10:26:20 AM UTC 24 |
| Peak memory | 202768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939538197 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1939538197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/101.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.616993696 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 187265295719 ps |
| CPU time | 390.96 seconds |
| Started | Oct 03 09:34:15 AM UTC 24 |
| Finished | Oct 03 09:40:52 AM UTC 24 |
| Peak memory | 201008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616993696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.616993696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/15.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.992702230 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 497224653020 ps |
| CPU time | 556.56 seconds |
| Started | Oct 03 09:34:16 AM UTC 24 |
| Finished | Oct 03 09:43:40 AM UTC 24 |
| Peak memory | 201056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992702230 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.992702230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.1058667331 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 199571868320 ps |
| CPU time | 540.19 seconds |
| Started | Oct 03 09:53:25 AM UTC 24 |
| Finished | Oct 03 10:02:32 AM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058667331 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.1058667331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/49.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.1043185534 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 293897775143 ps |
| CPU time | 839.59 seconds |
| Started | Oct 03 09:55:56 AM UTC 24 |
| Finished | Oct 03 10:10:07 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043185534 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1043185534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/66.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.2107982154 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1505718049632 ps |
| CPU time | 314.01 seconds |
| Started | Oct 03 09:57:37 AM UTC 24 |
| Finished | Oct 03 10:02:56 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107982154 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2107982154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/76.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.4081378221 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 93230022707 ps |
| CPU time | 289.75 seconds |
| Started | Oct 03 09:57:58 AM UTC 24 |
| Finished | Oct 03 10:02:52 AM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081378221 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4081378221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/77.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.764355621 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 165384665678 ps |
| CPU time | 554.27 seconds |
| Started | Oct 03 09:58:06 AM UTC 24 |
| Finished | Oct 03 10:07:28 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764355621 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.764355621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/79.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.3521597008 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 355664913252 ps |
| CPU time | 398.96 seconds |
| Started | Oct 03 10:01:24 AM UTC 24 |
| Finished | Oct 03 10:08:08 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521597008 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3521597008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/98.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2531569099 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 19997043 ps |
| CPU time | 0.67 seconds |
| Started | Oct 03 08:56:26 AM UTC 24 |
| Finished | Oct 03 08:56:28 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531569099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.2531569099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.4125774000 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1077745254041 ps |
| CPU time | 981.72 seconds |
| Started | Oct 03 10:03:13 AM UTC 24 |
| Finished | Oct 03 10:19:47 AM UTC 24 |
| Peak memory | 202960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125774000 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.4125774000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/109.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.3668920603 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 126663815215 ps |
| CPU time | 123.91 seconds |
| Started | Oct 03 09:34:06 AM UTC 24 |
| Finished | Oct 03 09:36:13 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668920603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3668920603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/11.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.722520675 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 126961633735 ps |
| CPU time | 148.11 seconds |
| Started | Oct 03 10:03:49 AM UTC 24 |
| Finished | Oct 03 10:06:20 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722520675 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.722520675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/111.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.3158608642 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 376133780486 ps |
| CPU time | 273.33 seconds |
| Started | Oct 03 09:34:13 AM UTC 24 |
| Finished | Oct 03 09:38:51 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158608642 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3158608642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/15.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.2089651059 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 476110950878 ps |
| CPU time | 2016.99 seconds |
| Started | Oct 03 09:54:56 AM UTC 24 |
| Finished | Oct 03 10:28:57 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089651059 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2089651059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/61.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.1111254424 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 101432051663 ps |
| CPU time | 147.26 seconds |
| Started | Oct 03 09:55:44 AM UTC 24 |
| Finished | Oct 03 09:58:13 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111254424 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1111254424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/63.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.3433643717 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 518698489686 ps |
| CPU time | 348.32 seconds |
| Started | Oct 03 09:58:25 AM UTC 24 |
| Finished | Oct 03 10:04:18 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433643717 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3433643717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/82.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.2559443743 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 292078819981 ps |
| CPU time | 420.87 seconds |
| Started | Oct 03 09:59:53 AM UTC 24 |
| Finished | Oct 03 10:07:01 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559443743 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2559443743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/91.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.586067021 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 78187112127 ps |
| CPU time | 61.73 seconds |
| Started | Oct 03 09:01:20 AM UTC 24 |
| Finished | Oct 03 09:02:24 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586067021 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.586067021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.1570032437 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 379164013608 ps |
| CPU time | 542.72 seconds |
| Started | Oct 03 10:02:43 AM UTC 24 |
| Finished | Oct 03 10:11:53 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570032437 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1570032437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/104.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.3910192366 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 152874360270 ps |
| CPU time | 262 seconds |
| Started | Oct 03 10:02:57 AM UTC 24 |
| Finished | Oct 03 10:07:23 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910192366 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3910192366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/107.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.1867722728 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 35303551164 ps |
| CPU time | 17.72 seconds |
| Started | Oct 03 10:03:54 AM UTC 24 |
| Finished | Oct 03 10:04:13 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867722728 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1867722728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/112.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.4117036176 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 142574670733 ps |
| CPU time | 647.76 seconds |
| Started | Oct 03 10:07:06 AM UTC 24 |
| Finished | Oct 03 10:18:03 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117036176 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4117036176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/135.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.3109692974 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 270819586953 ps |
| CPU time | 1085.54 seconds |
| Started | Oct 03 10:10:20 AM UTC 24 |
| Finished | Oct 03 10:28:38 AM UTC 24 |
| Peak memory | 203024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109692974 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3109692974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/153.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.3676217821 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 47383966127 ps |
| CPU time | 84.92 seconds |
| Started | Oct 03 10:10:49 AM UTC 24 |
| Finished | Oct 03 10:12:16 AM UTC 24 |
| Peak memory | 201208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676217821 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3676217821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/155.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.3930587779 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 70022774536 ps |
| CPU time | 496.41 seconds |
| Started | Oct 03 10:11:49 AM UTC 24 |
| Finished | Oct 03 10:20:12 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930587779 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3930587779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/160.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.2861983887 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1405038993169 ps |
| CPU time | 953.74 seconds |
| Started | Oct 03 10:11:49 AM UTC 24 |
| Finished | Oct 03 10:27:54 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861983887 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2861983887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/161.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.58628944 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 213755801886 ps |
| CPU time | 121.3 seconds |
| Started | Oct 03 10:11:50 AM UTC 24 |
| Finished | Oct 03 10:13:53 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58628944 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.58628944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/162.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.4083999538 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1238693924207 ps |
| CPU time | 484.29 seconds |
| Started | Oct 03 10:12:00 AM UTC 24 |
| Finished | Oct 03 10:20:11 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083999538 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4083999538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/164.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.4024064821 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 255115360292 ps |
| CPU time | 409.32 seconds |
| Started | Oct 03 10:13:45 AM UTC 24 |
| Finished | Oct 03 10:20:40 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024064821 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.4024064821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/180.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.3166394384 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 166524013873 ps |
| CPU time | 262.31 seconds |
| Started | Oct 03 10:13:54 AM UTC 24 |
| Finished | Oct 03 10:18:20 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166394384 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3166394384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/181.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.125748366 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 202006739304 ps |
| CPU time | 98.65 seconds |
| Started | Oct 03 10:15:00 AM UTC 24 |
| Finished | Oct 03 10:16:41 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125748366 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.125748366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/186.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.1031776494 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 119040446967 ps |
| CPU time | 120.33 seconds |
| Started | Oct 03 09:35:26 AM UTC 24 |
| Finished | Oct 03 09:37:28 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031776494 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.1031776494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.1732480139 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 38683965890 ps |
| CPU time | 81.38 seconds |
| Started | Oct 03 09:36:13 AM UTC 24 |
| Finished | Oct 03 09:37:37 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732480139 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.1732480139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.1468637356 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 5224398133371 ps |
| CPU time | 1529.41 seconds |
| Started | Oct 03 09:37:01 AM UTC 24 |
| Finished | Oct 03 10:02:49 AM UTC 24 |
| Peak memory | 202620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468637356 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.1468637356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.2690567947 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 455900489698 ps |
| CPU time | 318.71 seconds |
| Started | Oct 03 09:37:16 AM UTC 24 |
| Finished | Oct 03 09:42:40 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690567947 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2690567947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/24.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.2195107095 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 914081237768 ps |
| CPU time | 871.87 seconds |
| Started | Oct 03 09:40:13 AM UTC 24 |
| Finished | Oct 03 09:54:55 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195107095 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.2195107095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/28.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.3294925040 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 531113417363 ps |
| CPU time | 447.18 seconds |
| Started | Oct 03 09:43:07 AM UTC 24 |
| Finished | Oct 03 09:50:39 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294925040 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.3294925040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.3816872769 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 231880564657 ps |
| CPU time | 286.46 seconds |
| Started | Oct 03 09:47:14 AM UTC 24 |
| Finished | Oct 03 09:52:05 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816872769 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3816872769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/42.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.1711090127 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1085891830881 ps |
| CPU time | 625.58 seconds |
| Started | Oct 03 09:50:50 AM UTC 24 |
| Finished | Oct 03 10:01:23 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711090127 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.1711090127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.2901191131 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 396757780593 ps |
| CPU time | 584.43 seconds |
| Started | Oct 03 09:53:54 AM UTC 24 |
| Finished | Oct 03 10:03:47 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901191131 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2901191131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/52.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1038525147 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 202453209 ps |
| CPU time | 2.16 seconds |
| Started | Oct 03 08:56:25 AM UTC 24 |
| Finished | Oct 03 08:56:28 AM UTC 24 |
| Peak memory | 200680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038525147 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.1038525147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3345703591 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 16727652 ps |
| CPU time | 0.49 seconds |
| Started | Oct 03 08:56:25 AM UTC 24 |
| Finished | Oct 03 08:56:26 AM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345703591 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.3345703591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1654111775 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 26042983 ps |
| CPU time | 0.64 seconds |
| Started | Oct 03 08:56:26 AM UTC 24 |
| Finished | Oct 03 08:56:28 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1654111775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs r_mem_rw_with_rand_reset.1654111775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.2074079633 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 44762709 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:25 AM UTC 24 |
| Finished | Oct 03 08:56:27 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074079633 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2074079633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.2564844246 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 42450794 ps |
| CPU time | 0.51 seconds |
| Started | Oct 03 08:56:25 AM UTC 24 |
| Finished | Oct 03 08:56:26 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564844246 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2564844246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.2188226275 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 357546099 ps |
| CPU time | 2.5 seconds |
| Started | Oct 03 08:56:23 AM UTC 24 |
| Finished | Oct 03 08:56:26 AM UTC 24 |
| Peak memory | 200684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188226275 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2188226275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3108628298 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 66953123 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:28 AM UTC 24 |
| Finished | Oct 03 08:56:30 AM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108628298 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.3108628298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1454753070 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 190931674 ps |
| CPU time | 2.19 seconds |
| Started | Oct 03 08:56:28 AM UTC 24 |
| Finished | Oct 03 08:56:32 AM UTC 24 |
| Peak memory | 200752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454753070 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.1454753070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2397989546 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 42950439 ps |
| CPU time | 0.49 seconds |
| Started | Oct 03 08:56:27 AM UTC 24 |
| Finished | Oct 03 08:56:29 AM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397989546 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.2397989546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1188130473 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 48109404 ps |
| CPU time | 0.66 seconds |
| Started | Oct 03 08:56:30 AM UTC 24 |
| Finished | Oct 03 08:56:31 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1188130473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs r_mem_rw_with_rand_reset.1188130473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.1872847290 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 19440943 ps |
| CPU time | 0.52 seconds |
| Started | Oct 03 08:56:28 AM UTC 24 |
| Finished | Oct 03 08:56:30 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872847290 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1872847290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.277432012 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 50881686 ps |
| CPU time | 0.51 seconds |
| Started | Oct 03 08:56:27 AM UTC 24 |
| Finished | Oct 03 08:56:29 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277432012 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.277432012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.569352171 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 22403335 ps |
| CPU time | 0.58 seconds |
| Started | Oct 03 08:56:29 AM UTC 24 |
| Finished | Oct 03 08:56:30 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569352171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.569352171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.3732233126 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 61132577 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 08:56:27 AM UTC 24 |
| Finished | Oct 03 08:56:30 AM UTC 24 |
| Peak memory | 198692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732233126 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3732233126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2113927792 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 401474523 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 08:56:27 AM UTC 24 |
| Finished | Oct 03 08:56:29 AM UTC 24 |
| Peak memory | 198556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113927792 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.2113927792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3077395928 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 72881719 ps |
| CPU time | 0.96 seconds |
| Started | Oct 03 08:56:40 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3077395928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_c sr_mem_rw_with_rand_reset.3077395928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.1979174619 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 27073458 ps |
| CPU time | 0.56 seconds |
| Started | Oct 03 08:56:40 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979174619 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1979174619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.4093637361 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 16805246 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:40 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093637361 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.4093637361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3595670040 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 199352496 ps |
| CPU time | 0.74 seconds |
| Started | Oct 03 08:56:40 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595670040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.3595670040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.3058671464 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 289304103 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 08:56:40 AM UTC 24 |
| Finished | Oct 03 08:56:43 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058671464 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3058671464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2324561198 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 119774278 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 08:56:40 AM UTC 24 |
| Finished | Oct 03 08:56:43 AM UTC 24 |
| Peak memory | 198852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324561198 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.2324561198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3420388507 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 20989837 ps |
| CPU time | 0.83 seconds |
| Started | Oct 03 08:56:41 AM UTC 24 |
| Finished | Oct 03 08:56:43 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3420388507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_c sr_mem_rw_with_rand_reset.3420388507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.751347359 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 33658808 ps |
| CPU time | 0.6 seconds |
| Started | Oct 03 08:56:41 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 198360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751347359 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.751347359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.3481512546 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 30146540 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:41 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481512546 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3481512546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/11.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.606250509 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 100981769 ps |
| CPU time | 0.76 seconds |
| Started | Oct 03 08:56:41 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 198272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606250509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.606250509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.1070018932 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 175527396 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 08:56:40 AM UTC 24 |
| Finished | Oct 03 08:56:43 AM UTC 24 |
| Peak memory | 199096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070018932 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1070018932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4000158786 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 197101337 ps |
| CPU time | 0.9 seconds |
| Started | Oct 03 08:56:41 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000158786 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.4000158786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1424164088 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 62909926 ps |
| CPU time | 0.64 seconds |
| Started | Oct 03 08:56:41 AM UTC 24 |
| Finished | Oct 03 08:56:43 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1424164088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c sr_mem_rw_with_rand_reset.1424164088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.3934097647 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 19095698 ps |
| CPU time | 0.58 seconds |
| Started | Oct 03 08:56:41 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934097647 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3934097647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.376026517 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 106004915 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:41 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376026517 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.376026517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.210881711 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 19460494 ps |
| CPU time | 0.75 seconds |
| Started | Oct 03 08:56:41 AM UTC 24 |
| Finished | Oct 03 08:56:43 AM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210881711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.210881711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.791961092 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 133708770 ps |
| CPU time | 2.31 seconds |
| Started | Oct 03 08:56:41 AM UTC 24 |
| Finished | Oct 03 08:56:44 AM UTC 24 |
| Peak memory | 200880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791961092 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.791961092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1466346173 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 114710515 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 08:56:41 AM UTC 24 |
| Finished | Oct 03 08:56:43 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466346173 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.1466346173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1725694536 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 55082431 ps |
| CPU time | 0.85 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:44 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1725694536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c sr_mem_rw_with_rand_reset.1725694536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.1476560464 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 15601891 ps |
| CPU time | 0.58 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:44 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476560464 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1476560464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.3643244630 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 35019886 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:44 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643244630 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3643244630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/13.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.465949914 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 33865815 ps |
| CPU time | 0.58 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:44 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465949914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.465949914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.3977939925 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 123554916 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:45 AM UTC 24 |
| Peak memory | 200948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977939925 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3977939925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2332099699 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 389688666 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:44 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332099699 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.2332099699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.373827402 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 22546797 ps |
| CPU time | 0.65 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:44 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=373827402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_cs r_mem_rw_with_rand_reset.373827402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1852889974 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 89243133 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:44 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852889974 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1852889974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.300941663 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 74068482 ps |
| CPU time | 0.58 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:44 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300941663 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.300941663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/14.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3845712266 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 22625677 ps |
| CPU time | 0.68 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:44 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845712266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.3845712266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.2603123909 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 590475564 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:45 AM UTC 24 |
| Peak memory | 200744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603123909 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2603123909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2358011145 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 476517350 ps |
| CPU time | 0.96 seconds |
| Started | Oct 03 08:56:42 AM UTC 24 |
| Finished | Oct 03 08:56:44 AM UTC 24 |
| Peak memory | 198852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358011145 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.2358011145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1896382680 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 63595778 ps |
| CPU time | 0.64 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:45 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1896382680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.1896382680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.4154988565 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 33570882 ps |
| CPU time | 0.57 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:45 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154988565 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.4154988565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.1809446680 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 31241357 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:45 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809446680 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1809446680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/15.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4165129040 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 23679173 ps |
| CPU time | 0.59 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:45 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165129040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.4165129040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.455762156 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 77003077 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 08:56:43 AM UTC 24 |
| Finished | Oct 03 08:56:46 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455762156 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.455762156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4242197049 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 411895122 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 08:56:43 AM UTC 24 |
| Finished | Oct 03 08:56:46 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242197049 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.4242197049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.724186749 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 114427662 ps |
| CPU time | 0.84 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:46 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=724186749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_cs r_mem_rw_with_rand_reset.724186749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.2422922903 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 42082529 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:45 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422922903 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2422922903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1835739558 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 13701336 ps |
| CPU time | 0.59 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:45 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835739558 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1835739558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/16.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2931989140 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 31978449 ps |
| CPU time | 0.71 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:45 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931989140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.2931989140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.2435305631 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 107440414 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:46 AM UTC 24 |
| Peak memory | 199096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435305631 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2435305631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3036833433 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 131740081 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:46 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036833433 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.3036833433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2510752425 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 35110986 ps |
| CPU time | 0.65 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:46 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2510752425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_c sr_mem_rw_with_rand_reset.2510752425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.2373899012 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 22351107 ps |
| CPU time | 0.54 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:45 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373899012 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2373899012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.1420370684 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 19919533 ps |
| CPU time | 0.56 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:46 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420370684 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1420370684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/17.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1557300477 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 80836013 ps |
| CPU time | 0.61 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:46 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557300477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.1557300477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.2307380380 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 75719462 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307380380 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2307380380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2485786179 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 258912201 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 08:56:44 AM UTC 24 |
| Finished | Oct 03 08:56:46 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485786179 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.2485786179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1486755664 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 19262526 ps |
| CPU time | 0.65 seconds |
| Started | Oct 03 08:56:45 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1486755664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c sr_mem_rw_with_rand_reset.1486755664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.226314542 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 36350463 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:45 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226314542 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.226314542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.373897094 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 12748568 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:45 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373897094 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.373897094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/18.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.4280254553 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 27934272 ps |
| CPU time | 0.67 seconds |
| Started | Oct 03 08:56:45 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280254553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.4280254553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.579751 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 136488570 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 08:56:45 AM UTC 24 |
| Finished | Oct 03 08:56:48 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579751 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.579751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3643391049 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 170957973 ps |
| CPU time | 0.83 seconds |
| Started | Oct 03 08:56:45 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643391049 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.3643391049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.46357447 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 70768125 ps |
| CPU time | 0.84 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=46357447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr _mem_rw_with_rand_reset.46357447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.744097260 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 53093433 ps |
| CPU time | 0.56 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744097260 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.744097260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.898507706 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 19149405 ps |
| CPU time | 0.54 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898507706 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.898507706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/19.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2680091276 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 18685929 ps |
| CPU time | 0.74 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680091276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.2680091276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.2774022174 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 284632793 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 08:56:45 AM UTC 24 |
| Finished | Oct 03 08:56:48 AM UTC 24 |
| Peak memory | 199096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774022174 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2774022174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.623180221 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 60305954 ps |
| CPU time | 0.81 seconds |
| Started | Oct 03 08:56:45 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623180221 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.623180221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2214939332 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 139009031 ps |
| CPU time | 0.69 seconds |
| Started | Oct 03 08:56:31 AM UTC 24 |
| Finished | Oct 03 08:56:33 AM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214939332 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.2214939332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3265382353 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 281559346 ps |
| CPU time | 2.47 seconds |
| Started | Oct 03 08:56:31 AM UTC 24 |
| Finished | Oct 03 08:56:34 AM UTC 24 |
| Peak memory | 200740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265382353 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.3265382353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.247795634 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 14590847 ps |
| CPU time | 0.54 seconds |
| Started | Oct 03 08:56:30 AM UTC 24 |
| Finished | Oct 03 08:56:31 AM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247795634 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.247795634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2860303537 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 25906518 ps |
| CPU time | 0.73 seconds |
| Started | Oct 03 08:56:31 AM UTC 24 |
| Finished | Oct 03 08:56:33 AM UTC 24 |
| Peak memory | 198840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2860303537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_cs r_mem_rw_with_rand_reset.2860303537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.2686368336 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 41909300 ps |
| CPU time | 0.52 seconds |
| Started | Oct 03 08:56:31 AM UTC 24 |
| Finished | Oct 03 08:56:32 AM UTC 24 |
| Peak memory | 198800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686368336 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2686368336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2318930085 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 43055139 ps |
| CPU time | 0.48 seconds |
| Started | Oct 03 08:56:30 AM UTC 24 |
| Finished | Oct 03 08:56:31 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318930085 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2318930085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.329983434 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 81996974 ps |
| CPU time | 0.67 seconds |
| Started | Oct 03 08:56:31 AM UTC 24 |
| Finished | Oct 03 08:56:32 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329983434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.329983434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.3445507878 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 58650091 ps |
| CPU time | 2.68 seconds |
| Started | Oct 03 08:56:30 AM UTC 24 |
| Finished | Oct 03 08:56:33 AM UTC 24 |
| Peak memory | 200680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445507878 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3445507878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3838382400 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 263633080 ps |
| CPU time | 0.92 seconds |
| Started | Oct 03 08:56:30 AM UTC 24 |
| Finished | Oct 03 08:56:32 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838382400 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.3838382400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.4268854198 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 111599083 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268854198 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4268854198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/20.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.2803350635 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 176373537 ps |
| CPU time | 0.56 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803350635 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2803350635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/21.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.3308458519 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 40551956 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308458519 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3308458519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/22.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.839788326 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 22451411 ps |
| CPU time | 0.51 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839788326 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.839788326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/23.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.1235059000 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 11010102 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235059000 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1235059000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/24.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1883289086 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 16204049 ps |
| CPU time | 0.58 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883289086 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1883289086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/25.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.4077318040 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 30639032 ps |
| CPU time | 0.5 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077318040 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.4077318040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/26.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.3078112913 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 83994515 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:46 AM UTC 24 |
| Finished | Oct 03 08:56:47 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078112913 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3078112913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/27.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.2853938469 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 31588699 ps |
| CPU time | 0.58 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853938469 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2853938469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/28.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.1264988587 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 23458745 ps |
| CPU time | 0.5 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264988587 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1264988587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/29.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3371634158 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 14740287 ps |
| CPU time | 0.79 seconds |
| Started | Oct 03 08:56:33 AM UTC 24 |
| Finished | Oct 03 08:56:35 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371634158 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.3371634158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1548318108 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 413968175 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 08:56:33 AM UTC 24 |
| Finished | Oct 03 08:56:36 AM UTC 24 |
| Peak memory | 198812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548318108 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.1548318108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2834432533 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 11573103 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:32 AM UTC 24 |
| Finished | Oct 03 08:56:34 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834432533 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.2834432533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.107520243 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 64933230 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 08:56:33 AM UTC 24 |
| Finished | Oct 03 08:56:35 AM UTC 24 |
| Peak memory | 201024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=107520243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr _mem_rw_with_rand_reset.107520243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.2996213605 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 15763220 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:32 AM UTC 24 |
| Finished | Oct 03 08:56:34 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996213605 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2996213605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.1504466647 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 42640894 ps |
| CPU time | 0.51 seconds |
| Started | Oct 03 08:56:32 AM UTC 24 |
| Finished | Oct 03 08:56:34 AM UTC 24 |
| Peak memory | 198804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504466647 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1504466647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.24148547 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 149137593 ps |
| CPU time | 0.79 seconds |
| Started | Oct 03 08:56:33 AM UTC 24 |
| Finished | Oct 03 08:56:35 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24148547 -assert nopostproc + UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.24148547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.2314974843 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 58411000 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 08:56:32 AM UTC 24 |
| Finished | Oct 03 08:56:34 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314974843 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2314974843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3571055941 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 105407284 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 08:56:32 AM UTC 24 |
| Finished | Oct 03 08:56:34 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571055941 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.3571055941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.1134070526 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 40395781 ps |
| CPU time | 0.54 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134070526 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1134070526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/30.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.767195228 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 15913229 ps |
| CPU time | 0.54 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767195228 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.767195228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/31.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.650603051 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 11952759 ps |
| CPU time | 0.54 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650603051 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.650603051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/32.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.2945946548 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 21088820 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945946548 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2945946548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/33.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.3563586323 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 13610346 ps |
| CPU time | 0.56 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563586323 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3563586323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/34.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2181536843 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 34940793 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181536843 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2181536843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/35.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.3415179602 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 25216525 ps |
| CPU time | 0.57 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415179602 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3415179602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/36.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.1275161865 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 25443481 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275161865 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1275161865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/37.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.2104931752 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 27409987 ps |
| CPU time | 0.48 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104931752 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2104931752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/38.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.181175035 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 14265948 ps |
| CPU time | 0.56 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181175035 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.181175035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/39.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.902918177 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 37619650 ps |
| CPU time | 0.84 seconds |
| Started | Oct 03 08:56:36 AM UTC 24 |
| Finished | Oct 03 08:56:37 AM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902918177 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.902918177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1077611038 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 137268539 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 08:56:36 AM UTC 24 |
| Finished | Oct 03 08:56:38 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077611038 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.1077611038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.726012962 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 13609938 ps |
| CPU time | 0.61 seconds |
| Started | Oct 03 08:56:34 AM UTC 24 |
| Finished | Oct 03 08:56:36 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726012962 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.726012962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2162297590 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 63713971 ps |
| CPU time | 0.85 seconds |
| Started | Oct 03 08:56:36 AM UTC 24 |
| Finished | Oct 03 08:56:38 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2162297590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_cs r_mem_rw_with_rand_reset.2162297590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.95186644 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 14379482 ps |
| CPU time | 0.56 seconds |
| Started | Oct 03 08:56:35 AM UTC 24 |
| Finished | Oct 03 08:56:36 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95186644 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.95186644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.1718632113 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 13841403 ps |
| CPU time | 0.62 seconds |
| Started | Oct 03 08:56:34 AM UTC 24 |
| Finished | Oct 03 08:56:36 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718632113 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1718632113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2709928931 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 127876516 ps |
| CPU time | 0.7 seconds |
| Started | Oct 03 08:56:36 AM UTC 24 |
| Finished | Oct 03 08:56:37 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709928931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.2709928931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.419315520 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 181132312 ps |
| CPU time | 2.16 seconds |
| Started | Oct 03 08:56:34 AM UTC 24 |
| Finished | Oct 03 08:56:37 AM UTC 24 |
| Peak memory | 202724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419315520 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.419315520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3418978215 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 113060685 ps |
| CPU time | 0.8 seconds |
| Started | Oct 03 08:56:34 AM UTC 24 |
| Finished | Oct 03 08:56:36 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418978215 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.3418978215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2799732503 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 38815652 ps |
| CPU time | 0.51 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799732503 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2799732503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/40.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.4232787410 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 13877458 ps |
| CPU time | 0.5 seconds |
| Started | Oct 03 08:56:47 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232787410 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.4232787410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/41.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.259439555 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 13717776 ps |
| CPU time | 0.54 seconds |
| Started | Oct 03 08:56:48 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259439555 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.259439555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/42.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.4035404853 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 42345186 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:48 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035404853 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4035404853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/43.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.2851850534 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 28304278 ps |
| CPU time | 0.52 seconds |
| Started | Oct 03 08:56:48 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851850534 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2851850534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/44.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.2185610163 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 51703494 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:48 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185610163 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2185610163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/45.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.4055925168 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 64328161 ps |
| CPU time | 0.5 seconds |
| Started | Oct 03 08:56:48 AM UTC 24 |
| Finished | Oct 03 08:56:49 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055925168 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.4055925168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/46.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.192490119 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 15594920 ps |
| CPU time | 0.52 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 08:56:50 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192490119 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.192490119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/47.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.3496565400 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 46130969 ps |
| CPU time | 0.58 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 08:56:50 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496565400 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3496565400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/48.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.883680590 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 13019154 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:49 AM UTC 24 |
| Finished | Oct 03 08:56:50 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883680590 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.883680590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/49.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.4091587335 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 61977861 ps |
| CPU time | 0.83 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 198840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4091587335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.4091587335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.2386086552 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 17133932 ps |
| CPU time | 0.59 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386086552 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2386086552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.2792598918 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 37240772 ps |
| CPU time | 0.56 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792598918 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2792598918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1052671381 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 35979995 ps |
| CPU time | 0.71 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052671381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.1052671381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.2413322381 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 40026964 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 08:56:36 AM UTC 24 |
| Finished | Oct 03 08:56:38 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413322381 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2413322381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3872836838 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 332861728 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 08:56:36 AM UTC 24 |
| Finished | Oct 03 08:56:38 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872836838 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.3872836838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1857952630 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 39235286 ps |
| CPU time | 0.91 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1857952630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_cs r_mem_rw_with_rand_reset.1857952630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.1225957444 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 15699254 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225957444 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1225957444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.3541096721 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 22679694 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541096721 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3541096721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/6.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.920624222 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 136399237 ps |
| CPU time | 0.75 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920624222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.920624222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.3854261084 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 551317497 ps |
| CPU time | 2.48 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:41 AM UTC 24 |
| Peak memory | 200896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854261084 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3854261084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1776930452 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 90556290 ps |
| CPU time | 0.81 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776930452 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.1776930452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2217297696 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 33844238 ps |
| CPU time | 0.71 seconds |
| Started | Oct 03 08:56:38 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2217297696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_cs r_mem_rw_with_rand_reset.2217297696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.2261951588 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 16527202 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:38 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261951588 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2261951588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.2773674775 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 37334497 ps |
| CPU time | 0.54 seconds |
| Started | Oct 03 08:56:38 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773674775 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2773674775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.106629973 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 64404047 ps |
| CPU time | 0.57 seconds |
| Started | Oct 03 08:56:38 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106629973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.106629973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.3397304390 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 218233843 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 08:56:37 AM UTC 24 |
| Finished | Oct 03 08:56:40 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397304390 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3397304390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1425055567 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 107967834 ps |
| CPU time | 0.77 seconds |
| Started | Oct 03 08:56:39 AM UTC 24 |
| Finished | Oct 03 08:56:41 AM UTC 24 |
| Peak memory | 198424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1425055567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.1425055567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.3571453553 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 39743756 ps |
| CPU time | 0.59 seconds |
| Started | Oct 03 08:56:39 AM UTC 24 |
| Finished | Oct 03 08:56:40 AM UTC 24 |
| Peak memory | 198468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571453553 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3571453553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.3947367231 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 53848561 ps |
| CPU time | 0.63 seconds |
| Started | Oct 03 08:56:39 AM UTC 24 |
| Finished | Oct 03 08:56:40 AM UTC 24 |
| Peak memory | 198800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947367231 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3947367231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/8.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4000330801 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 24184840 ps |
| CPU time | 0.61 seconds |
| Started | Oct 03 08:56:39 AM UTC 24 |
| Finished | Oct 03 08:56:40 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000330801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.4000330801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.1439147092 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 93675777 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 08:56:38 AM UTC 24 |
| Finished | Oct 03 08:56:40 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439147092 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1439147092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3337456769 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 143282967 ps |
| CPU time | 0.76 seconds |
| Started | Oct 03 08:56:38 AM UTC 24 |
| Finished | Oct 03 08:56:39 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337456769 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.3337456769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3837116487 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 58114900 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 08:56:40 AM UTC 24 |
| Finished | Oct 03 08:56:43 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3837116487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_cs r_mem_rw_with_rand_reset.3837116487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.3636315103 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 16282044 ps |
| CPU time | 0.55 seconds |
| Started | Oct 03 08:56:39 AM UTC 24 |
| Finished | Oct 03 08:56:41 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636315103 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3636315103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.1689128594 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 35118105 ps |
| CPU time | 0.53 seconds |
| Started | Oct 03 08:56:39 AM UTC 24 |
| Finished | Oct 03 08:56:41 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689128594 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1689128594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/9.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2279916181 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 76541320 ps |
| CPU time | 0.65 seconds |
| Started | Oct 03 08:56:40 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279916181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.2279916181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.834800507 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 274436996 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 08:56:39 AM UTC 24 |
| Finished | Oct 03 08:56:42 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834800507 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.834800507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.58603168 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 988234584 ps |
| CPU time | 0.85 seconds |
| Started | Oct 03 08:56:39 AM UTC 24 |
| Finished | Oct 03 08:56:41 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58603168 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.58603168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.2828910720 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 148098329017 ps |
| CPU time | 345.2 seconds |
| Started | Oct 03 08:57:18 AM UTC 24 |
| Finished | Oct 03 09:03:09 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828910720 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.2828910720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.4027104873 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 48095124182 ps |
| CPU time | 94.55 seconds |
| Started | Oct 03 08:57:15 AM UTC 24 |
| Finished | Oct 03 08:58:53 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027104873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.4027104873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.1014602965 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 23882115324 ps |
| CPU time | 53.24 seconds |
| Started | Oct 03 08:57:21 AM UTC 24 |
| Finished | Oct 03 08:58:16 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014602965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1014602965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.1729533591 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 876286531486 ps |
| CPU time | 940.11 seconds |
| Started | Oct 03 08:57:34 AM UTC 24 |
| Finished | Oct 03 09:13:29 AM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729533591 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.1729533591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/0.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.1621279606 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 121198058974 ps |
| CPU time | 199.77 seconds |
| Started | Oct 03 08:58:53 AM UTC 24 |
| Finished | Oct 03 09:02:16 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621279606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1621279606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.2574291347 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 141885174264 ps |
| CPU time | 79.8 seconds |
| Started | Oct 03 09:01:21 AM UTC 24 |
| Finished | Oct 03 09:02:43 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574291347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2574291347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.904467036 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 297165277 ps |
| CPU time | 1.03 seconds |
| Started | Oct 03 09:02:44 AM UTC 24 |
| Finished | Oct 03 09:02:46 AM UTC 24 |
| Peak memory | 232592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904467036 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.904467036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.2180073382 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 353756835830 ps |
| CPU time | 523.81 seconds |
| Started | Oct 03 09:34:05 AM UTC 24 |
| Finished | Oct 03 09:42:55 AM UTC 24 |
| Peak memory | 202776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180073382 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.2180073382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.3977447736 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 271619764893 ps |
| CPU time | 201.79 seconds |
| Started | Oct 03 09:34:05 AM UTC 24 |
| Finished | Oct 03 09:37:30 AM UTC 24 |
| Peak memory | 200916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977447736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3977447736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.3985239350 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 38379819973 ps |
| CPU time | 85.82 seconds |
| Started | Oct 03 09:34:04 AM UTC 24 |
| Finished | Oct 03 09:35:32 AM UTC 24 |
| Peak memory | 200720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985239350 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3985239350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.3871598394 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 69367479 ps |
| CPU time | 0.92 seconds |
| Started | Oct 03 09:34:05 AM UTC 24 |
| Finished | Oct 03 09:34:07 AM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871598394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3871598394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.4137061527 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 417061544553 ps |
| CPU time | 957.11 seconds |
| Started | Oct 03 09:34:05 AM UTC 24 |
| Finished | Oct 03 09:50:13 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137061527 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.4137061527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all_with_rand_reset.924275998 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1055534148 ps |
| CPU time | 10.02 seconds |
| Started | Oct 03 09:34:05 AM UTC 24 |
| Finished | Oct 03 09:34:16 AM UTC 24 |
| Peak memory | 203180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=924275998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.924275998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/10.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.2519400353 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 567052437869 ps |
| CPU time | 843.24 seconds |
| Started | Oct 03 10:01:34 AM UTC 24 |
| Finished | Oct 03 10:15:48 AM UTC 24 |
| Peak memory | 202700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519400353 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2519400353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/100.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.632434527 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 262628644849 ps |
| CPU time | 503.64 seconds |
| Started | Oct 03 10:02:18 AM UTC 24 |
| Finished | Oct 03 10:10:48 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632434527 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.632434527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/102.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.4034513610 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 90214602719 ps |
| CPU time | 304.67 seconds |
| Started | Oct 03 10:02:50 AM UTC 24 |
| Finished | Oct 03 10:08:00 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034513610 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.4034513610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/105.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.908290069 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 53654948349 ps |
| CPU time | 96.67 seconds |
| Started | Oct 03 10:02:53 AM UTC 24 |
| Finished | Oct 03 10:04:32 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908290069 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.908290069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/106.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.1973251796 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2591873148347 ps |
| CPU time | 1089.94 seconds |
| Started | Oct 03 09:34:06 AM UTC 24 |
| Finished | Oct 03 09:52:29 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973251796 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.1973251796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.1639043448 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 178763884889 ps |
| CPU time | 361.34 seconds |
| Started | Oct 03 09:34:05 AM UTC 24 |
| Finished | Oct 03 09:40:12 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639043448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1639043448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/11.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.540060220 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 15875114002 ps |
| CPU time | 42.91 seconds |
| Started | Oct 03 09:34:05 AM UTC 24 |
| Finished | Oct 03 09:34:50 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540060220 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.540060220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/11.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.3695859529 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 43883748391 ps |
| CPU time | 34.29 seconds |
| Started | Oct 03 10:04:04 AM UTC 24 |
| Finished | Oct 03 10:04:40 AM UTC 24 |
| Peak memory | 201208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695859529 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3695859529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/113.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.2385328018 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 130400994194 ps |
| CPU time | 133.33 seconds |
| Started | Oct 03 10:04:14 AM UTC 24 |
| Finished | Oct 03 10:06:30 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385328018 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2385328018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/114.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.3776457162 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 37185863565 ps |
| CPU time | 55.23 seconds |
| Started | Oct 03 10:04:18 AM UTC 24 |
| Finished | Oct 03 10:05:15 AM UTC 24 |
| Peak memory | 201252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776457162 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3776457162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/115.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.3652221041 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 458810017115 ps |
| CPU time | 1087.6 seconds |
| Started | Oct 03 10:04:33 AM UTC 24 |
| Finished | Oct 03 10:22:53 AM UTC 24 |
| Peak memory | 202768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652221041 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3652221041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/116.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.4082988610 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 551362066530 ps |
| CPU time | 839.5 seconds |
| Started | Oct 03 10:04:33 AM UTC 24 |
| Finished | Oct 03 10:18:42 AM UTC 24 |
| Peak memory | 202960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082988610 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4082988610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/117.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.1303213850 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 146043371112 ps |
| CPU time | 272.09 seconds |
| Started | Oct 03 10:04:35 AM UTC 24 |
| Finished | Oct 03 10:09:11 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303213850 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1303213850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/118.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.3928462465 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 316985359645 ps |
| CPU time | 494.72 seconds |
| Started | Oct 03 10:04:41 AM UTC 24 |
| Finished | Oct 03 10:13:02 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928462465 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3928462465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/119.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.4189713497 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 20275935974 ps |
| CPU time | 13.7 seconds |
| Started | Oct 03 09:34:07 AM UTC 24 |
| Finished | Oct 03 09:34:21 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189713497 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.4189713497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.3627720973 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 117905027511 ps |
| CPU time | 130.44 seconds |
| Started | Oct 03 09:34:06 AM UTC 24 |
| Finished | Oct 03 09:36:20 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627720973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3627720973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.3028386973 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 6217071203 ps |
| CPU time | 9.09 seconds |
| Started | Oct 03 09:34:06 AM UTC 24 |
| Finished | Oct 03 09:34:17 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028386973 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3028386973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.771243736 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 64213472926 ps |
| CPU time | 168.87 seconds |
| Started | Oct 03 09:34:07 AM UTC 24 |
| Finished | Oct 03 09:36:59 AM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771243736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.771243736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all_with_rand_reset.3073849310 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4701698779 ps |
| CPU time | 33.98 seconds |
| Started | Oct 03 09:34:08 AM UTC 24 |
| Finished | Oct 03 09:34:44 AM UTC 24 |
| Peak memory | 205040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3073849310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.rv_timer_stress_all_with_rand_reset.3073849310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/12.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.781072455 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 477914675407 ps |
| CPU time | 2645.69 seconds |
| Started | Oct 03 10:05:07 AM UTC 24 |
| Finished | Oct 03 10:49:45 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781072455 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.781072455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/120.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.3180264702 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 798469236030 ps |
| CPU time | 1045.37 seconds |
| Started | Oct 03 10:05:12 AM UTC 24 |
| Finished | Oct 03 10:22:50 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180264702 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3180264702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/121.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.2759213723 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 50219016507 ps |
| CPU time | 131.7 seconds |
| Started | Oct 03 10:05:16 AM UTC 24 |
| Finished | Oct 03 10:07:30 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759213723 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2759213723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/122.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.1094416262 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 113563976919 ps |
| CPU time | 1387.19 seconds |
| Started | Oct 03 10:05:42 AM UTC 24 |
| Finished | Oct 03 10:29:06 AM UTC 24 |
| Peak memory | 202960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094416262 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1094416262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/124.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.1387464677 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 226952888037 ps |
| CPU time | 184.76 seconds |
| Started | Oct 03 10:05:53 AM UTC 24 |
| Finished | Oct 03 10:09:01 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387464677 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1387464677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/125.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.216396152 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 9578671084 ps |
| CPU time | 29.47 seconds |
| Started | Oct 03 10:06:06 AM UTC 24 |
| Finished | Oct 03 10:06:36 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216396152 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.216396152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/126.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.2704013841 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 161157754053 ps |
| CPU time | 674.98 seconds |
| Started | Oct 03 10:06:09 AM UTC 24 |
| Finished | Oct 03 10:17:32 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704013841 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2704013841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/127.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.2275016064 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 405348576386 ps |
| CPU time | 522.82 seconds |
| Started | Oct 03 10:06:11 AM UTC 24 |
| Finished | Oct 03 10:15:00 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275016064 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2275016064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/128.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.855282748 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 126698436353 ps |
| CPU time | 322.68 seconds |
| Started | Oct 03 10:06:21 AM UTC 24 |
| Finished | Oct 03 10:11:48 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855282748 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.855282748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/129.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.1436843130 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 279670419844 ps |
| CPU time | 593.37 seconds |
| Started | Oct 03 09:34:09 AM UTC 24 |
| Finished | Oct 03 09:44:10 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436843130 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.1436843130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.1582887609 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 227678823687 ps |
| CPU time | 148.06 seconds |
| Started | Oct 03 09:34:08 AM UTC 24 |
| Finished | Oct 03 09:36:39 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582887609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1582887609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/13.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.2815661486 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 59162366809 ps |
| CPU time | 154.14 seconds |
| Started | Oct 03 09:34:08 AM UTC 24 |
| Finished | Oct 03 09:36:45 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815661486 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2815661486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/13.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.738016021 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 645460612692 ps |
| CPU time | 2493.22 seconds |
| Started | Oct 03 09:34:09 AM UTC 24 |
| Finished | Oct 03 10:16:11 AM UTC 24 |
| Peak memory | 202700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738016021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.738016021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/13.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.2602021233 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 95198886674 ps |
| CPU time | 170.1 seconds |
| Started | Oct 03 10:06:24 AM UTC 24 |
| Finished | Oct 03 10:09:18 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602021233 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2602021233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/130.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.95001905 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 86704898237 ps |
| CPU time | 514.57 seconds |
| Started | Oct 03 10:06:31 AM UTC 24 |
| Finished | Oct 03 10:15:13 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95001905 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.95001905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/131.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.4182734000 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 810972930106 ps |
| CPU time | 932.47 seconds |
| Started | Oct 03 10:06:37 AM UTC 24 |
| Finished | Oct 03 10:22:21 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182734000 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.4182734000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/132.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.2135086952 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 122857583425 ps |
| CPU time | 556.38 seconds |
| Started | Oct 03 10:06:47 AM UTC 24 |
| Finished | Oct 03 10:16:11 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135086952 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2135086952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/133.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.1577370445 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1268978760 ps |
| CPU time | 3.23 seconds |
| Started | Oct 03 10:07:01 AM UTC 24 |
| Finished | Oct 03 10:07:06 AM UTC 24 |
| Peak memory | 200860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577370445 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1577370445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/134.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.2700498810 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 119191985900 ps |
| CPU time | 286.76 seconds |
| Started | Oct 03 10:07:08 AM UTC 24 |
| Finished | Oct 03 10:11:59 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700498810 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2700498810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/136.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.1564862756 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 347405042077 ps |
| CPU time | 226.69 seconds |
| Started | Oct 03 10:07:24 AM UTC 24 |
| Finished | Oct 03 10:11:14 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564862756 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1564862756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/137.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.353135963 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 321196275997 ps |
| CPU time | 456.53 seconds |
| Started | Oct 03 10:07:29 AM UTC 24 |
| Finished | Oct 03 10:15:12 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353135963 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.353135963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/138.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.2479033436 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 123670250489 ps |
| CPU time | 293.63 seconds |
| Started | Oct 03 10:07:31 AM UTC 24 |
| Finished | Oct 03 10:12:28 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479033436 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2479033436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/139.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.2095072297 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 90779644145 ps |
| CPU time | 136.91 seconds |
| Started | Oct 03 09:34:11 AM UTC 24 |
| Finished | Oct 03 09:36:32 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095072297 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.2095072297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.4151470449 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 220979884250 ps |
| CPU time | 313.78 seconds |
| Started | Oct 03 09:34:10 AM UTC 24 |
| Finished | Oct 03 09:39:28 AM UTC 24 |
| Peak memory | 201060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151470449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4151470449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/14.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.3317940550 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 342117115389 ps |
| CPU time | 294 seconds |
| Started | Oct 03 09:34:10 AM UTC 24 |
| Finished | Oct 03 09:39:08 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317940550 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3317940550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/14.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.1729368054 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 136153259745 ps |
| CPU time | 422.58 seconds |
| Started | Oct 03 09:34:11 AM UTC 24 |
| Finished | Oct 03 09:41:21 AM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729368054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1729368054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/14.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.1534079695 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 99859319378 ps |
| CPU time | 229.32 seconds |
| Started | Oct 03 10:07:51 AM UTC 24 |
| Finished | Oct 03 10:11:44 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534079695 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1534079695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/140.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.4231851116 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 45209116927 ps |
| CPU time | 254.23 seconds |
| Started | Oct 03 10:08:00 AM UTC 24 |
| Finished | Oct 03 10:12:19 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231851116 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4231851116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/141.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.4072225524 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 233383332000 ps |
| CPU time | 424.31 seconds |
| Started | Oct 03 10:08:21 AM UTC 24 |
| Finished | Oct 03 10:15:31 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072225524 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.4072225524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/143.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.656536844 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 89987966592 ps |
| CPU time | 141.98 seconds |
| Started | Oct 03 10:08:27 AM UTC 24 |
| Finished | Oct 03 10:10:52 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656536844 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.656536844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/144.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.3511456606 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 251808835506 ps |
| CPU time | 363.93 seconds |
| Started | Oct 03 10:08:50 AM UTC 24 |
| Finished | Oct 03 10:14:59 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511456606 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3511456606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/146.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.2363293767 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 79238286156 ps |
| CPU time | 1961.1 seconds |
| Started | Oct 03 10:09:02 AM UTC 24 |
| Finished | Oct 03 10:42:05 AM UTC 24 |
| Peak memory | 202768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363293767 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2363293767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/147.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.3668640485 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 690939089133 ps |
| CPU time | 571.03 seconds |
| Started | Oct 03 10:09:12 AM UTC 24 |
| Finished | Oct 03 10:18:51 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668640485 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3668640485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/148.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.1256762708 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 48045032431 ps |
| CPU time | 147.68 seconds |
| Started | Oct 03 10:09:17 AM UTC 24 |
| Finished | Oct 03 10:11:47 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256762708 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1256762708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/149.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.2996428747 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 300470931152 ps |
| CPU time | 631.87 seconds |
| Started | Oct 03 09:34:15 AM UTC 24 |
| Finished | Oct 03 09:44:55 AM UTC 24 |
| Peak memory | 201284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996428747 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.2996428747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.1172161859 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 883608570 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 09:34:13 AM UTC 24 |
| Finished | Oct 03 09:34:16 AM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172161859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1172161859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/15.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.22104255 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 499950154189 ps |
| CPU time | 1085.36 seconds |
| Started | Oct 03 09:34:15 AM UTC 24 |
| Finished | Oct 03 09:52:33 AM UTC 24 |
| Peak memory | 202960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22104255 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.22104255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/15.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.3132466390 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 108400710840 ps |
| CPU time | 240.1 seconds |
| Started | Oct 03 10:09:18 AM UTC 24 |
| Finished | Oct 03 10:13:22 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132466390 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3132466390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/150.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.1217781960 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 1225051396320 ps |
| CPU time | 356.47 seconds |
| Started | Oct 03 10:09:51 AM UTC 24 |
| Finished | Oct 03 10:15:53 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217781960 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1217781960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/151.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.1290366248 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 80045413886 ps |
| CPU time | 110.17 seconds |
| Started | Oct 03 10:10:07 AM UTC 24 |
| Finished | Oct 03 10:12:00 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290366248 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1290366248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/152.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.2297144047 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 37466898604 ps |
| CPU time | 177.82 seconds |
| Started | Oct 03 10:10:33 AM UTC 24 |
| Finished | Oct 03 10:13:34 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297144047 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2297144047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/154.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.4250378615 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 567029682626 ps |
| CPU time | 725.01 seconds |
| Started | Oct 03 10:10:53 AM UTC 24 |
| Finished | Oct 03 10:23:07 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250378615 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.4250378615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/156.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.2459313422 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 23961443028 ps |
| CPU time | 68.48 seconds |
| Started | Oct 03 10:11:08 AM UTC 24 |
| Finished | Oct 03 10:12:18 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459313422 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2459313422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/157.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.3428148138 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 170995383057 ps |
| CPU time | 271.24 seconds |
| Started | Oct 03 10:11:14 AM UTC 24 |
| Finished | Oct 03 10:15:50 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428148138 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3428148138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/158.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.1947190559 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 18286146343 ps |
| CPU time | 22.12 seconds |
| Started | Oct 03 10:11:45 AM UTC 24 |
| Finished | Oct 03 10:12:09 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947190559 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1947190559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/159.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.1513203045 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 26574439836 ps |
| CPU time | 170.1 seconds |
| Started | Oct 03 09:34:15 AM UTC 24 |
| Finished | Oct 03 09:37:09 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513203045 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1513203045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/16.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.2094781356 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 300220945 ps |
| CPU time | 0.9 seconds |
| Started | Oct 03 09:34:17 AM UTC 24 |
| Finished | Oct 03 09:34:20 AM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094781356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2094781356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/16.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.588797416 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1535564217338 ps |
| CPU time | 398.95 seconds |
| Started | Oct 03 09:34:18 AM UTC 24 |
| Finished | Oct 03 09:41:03 AM UTC 24 |
| Peak memory | 200876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588797416 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.588797416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/16.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.1664493605 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 115410833733 ps |
| CPU time | 91.2 seconds |
| Started | Oct 03 10:11:54 AM UTC 24 |
| Finished | Oct 03 10:13:27 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664493605 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1664493605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/163.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.3879782580 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 230732942121 ps |
| CPU time | 3340.95 seconds |
| Started | Oct 03 10:12:09 AM UTC 24 |
| Finished | Oct 03 11:08:35 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879782580 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3879782580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/166.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.526461048 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 567863408434 ps |
| CPU time | 577.15 seconds |
| Started | Oct 03 10:12:10 AM UTC 24 |
| Finished | Oct 03 10:21:55 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526461048 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.526461048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/167.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.2584052548 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 55132599521 ps |
| CPU time | 212.23 seconds |
| Started | Oct 03 10:12:16 AM UTC 24 |
| Finished | Oct 03 10:15:52 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584052548 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2584052548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/168.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.2272817990 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 62152979931 ps |
| CPU time | 371.23 seconds |
| Started | Oct 03 10:12:19 AM UTC 24 |
| Finished | Oct 03 10:18:36 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272817990 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2272817990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/169.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.3353148088 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 21045562674 ps |
| CPU time | 37.39 seconds |
| Started | Oct 03 09:34:19 AM UTC 24 |
| Finished | Oct 03 09:34:58 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353148088 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.3353148088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.391783185 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 577029932471 ps |
| CPU time | 315.14 seconds |
| Started | Oct 03 09:34:18 AM UTC 24 |
| Finished | Oct 03 09:39:38 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391783185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.391783185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/17.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.2497534769 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 683601320524 ps |
| CPU time | 741.11 seconds |
| Started | Oct 03 09:34:18 AM UTC 24 |
| Finished | Oct 03 09:46:48 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497534769 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2497534769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/17.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.555044157 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 24177566 ps |
| CPU time | 0.89 seconds |
| Started | Oct 03 09:34:19 AM UTC 24 |
| Finished | Oct 03 09:34:21 AM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555044157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.555044157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/17.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.1446846158 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 1392812773001 ps |
| CPU time | 792.06 seconds |
| Started | Oct 03 10:12:19 AM UTC 24 |
| Finished | Oct 03 10:25:42 AM UTC 24 |
| Peak memory | 201364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446846158 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1446846158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/170.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.2462798111 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 72182532379 ps |
| CPU time | 880.96 seconds |
| Started | Oct 03 10:12:30 AM UTC 24 |
| Finished | Oct 03 10:27:21 AM UTC 24 |
| Peak memory | 202960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462798111 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2462798111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/171.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.4069560062 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 222132038618 ps |
| CPU time | 186.94 seconds |
| Started | Oct 03 10:12:58 AM UTC 24 |
| Finished | Oct 03 10:16:08 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069560062 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.4069560062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/172.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.1460363361 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 810113460270 ps |
| CPU time | 814.87 seconds |
| Started | Oct 03 10:13:18 AM UTC 24 |
| Finished | Oct 03 10:27:03 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460363361 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1460363361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/175.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.3482393736 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 246384952000 ps |
| CPU time | 359.36 seconds |
| Started | Oct 03 10:13:23 AM UTC 24 |
| Finished | Oct 03 10:19:28 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482393736 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3482393736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/176.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.4267375495 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 81730546518 ps |
| CPU time | 188.44 seconds |
| Started | Oct 03 10:13:28 AM UTC 24 |
| Finished | Oct 03 10:16:40 AM UTC 24 |
| Peak memory | 201272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267375495 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.4267375495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/177.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.81019753 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 114670042685 ps |
| CPU time | 1524.16 seconds |
| Started | Oct 03 10:13:33 AM UTC 24 |
| Finished | Oct 03 10:39:16 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81019753 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.81019753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/178.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.124226042 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 244615401424 ps |
| CPU time | 166.16 seconds |
| Started | Oct 03 10:13:34 AM UTC 24 |
| Finished | Oct 03 10:16:24 AM UTC 24 |
| Peak memory | 201008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124226042 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.124226042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/179.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.2917149454 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 85740936014 ps |
| CPU time | 229.19 seconds |
| Started | Oct 03 09:34:22 AM UTC 24 |
| Finished | Oct 03 09:38:16 AM UTC 24 |
| Peak memory | 201020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917149454 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.2917149454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.1173290293 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 36452642544 ps |
| CPU time | 100.53 seconds |
| Started | Oct 03 09:34:22 AM UTC 24 |
| Finished | Oct 03 09:36:05 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173290293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1173290293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/18.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.262919039 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 48335951100 ps |
| CPU time | 157.21 seconds |
| Started | Oct 03 09:34:21 AM UTC 24 |
| Finished | Oct 03 09:37:02 AM UTC 24 |
| Peak memory | 201100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262919039 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.262919039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/18.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.176288240 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 239380501288 ps |
| CPU time | 157.74 seconds |
| Started | Oct 03 09:34:27 AM UTC 24 |
| Finished | Oct 03 09:37:07 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176288240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.176288240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/18.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.1839338905 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 96236194911 ps |
| CPU time | 179.07 seconds |
| Started | Oct 03 10:13:56 AM UTC 24 |
| Finished | Oct 03 10:16:58 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839338905 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1839338905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/182.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.1810050971 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2712252989634 ps |
| CPU time | 706.92 seconds |
| Started | Oct 03 10:14:45 AM UTC 24 |
| Finished | Oct 03 10:26:41 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810050971 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1810050971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/183.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.2948369187 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 64691385024 ps |
| CPU time | 369.96 seconds |
| Started | Oct 03 10:14:53 AM UTC 24 |
| Finished | Oct 03 10:21:08 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948369187 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2948369187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/184.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.1996914191 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 83648974242 ps |
| CPU time | 224.74 seconds |
| Started | Oct 03 10:14:59 AM UTC 24 |
| Finished | Oct 03 10:18:47 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996914191 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1996914191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/185.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.1546809585 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 204020293330 ps |
| CPU time | 29.3 seconds |
| Started | Oct 03 10:15:11 AM UTC 24 |
| Finished | Oct 03 10:15:42 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546809585 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1546809585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/187.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.1072363440 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 204644389256 ps |
| CPU time | 424.33 seconds |
| Started | Oct 03 10:15:13 AM UTC 24 |
| Finished | Oct 03 10:22:23 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072363440 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1072363440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/188.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.1894386705 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 361928653390 ps |
| CPU time | 819.14 seconds |
| Started | Oct 03 10:15:14 AM UTC 24 |
| Finished | Oct 03 10:29:03 AM UTC 24 |
| Peak memory | 203024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894386705 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1894386705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/189.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.596248051 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 20452694847 ps |
| CPU time | 44.14 seconds |
| Started | Oct 03 09:34:44 AM UTC 24 |
| Finished | Oct 03 09:35:30 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596248051 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.596248051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.3768744951 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 147581500186 ps |
| CPU time | 361.12 seconds |
| Started | Oct 03 09:34:37 AM UTC 24 |
| Finished | Oct 03 09:40:44 AM UTC 24 |
| Peak memory | 200988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768744951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3768744951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/19.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.117027159 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 165023316586 ps |
| CPU time | 464.59 seconds |
| Started | Oct 03 09:34:32 AM UTC 24 |
| Finished | Oct 03 09:42:24 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117027159 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.117027159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/19.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.3954989256 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 25530593231 ps |
| CPU time | 87.86 seconds |
| Started | Oct 03 09:34:50 AM UTC 24 |
| Finished | Oct 03 09:36:20 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954989256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3954989256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/19.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.1151580970 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 17538236858 ps |
| CPU time | 27.48 seconds |
| Started | Oct 03 10:15:32 AM UTC 24 |
| Finished | Oct 03 10:16:01 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151580970 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1151580970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/190.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.1763951416 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 374499767275 ps |
| CPU time | 283.07 seconds |
| Started | Oct 03 10:15:43 AM UTC 24 |
| Finished | Oct 03 10:20:30 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763951416 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1763951416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/191.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.403621599 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 105750748302 ps |
| CPU time | 349.7 seconds |
| Started | Oct 03 10:15:51 AM UTC 24 |
| Finished | Oct 03 10:21:45 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403621599 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.403621599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/193.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.3026074676 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 123726792676 ps |
| CPU time | 310.82 seconds |
| Started | Oct 03 10:15:53 AM UTC 24 |
| Finished | Oct 03 10:21:08 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026074676 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3026074676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/194.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.2292220324 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 135809655216 ps |
| CPU time | 254.39 seconds |
| Started | Oct 03 10:16:01 AM UTC 24 |
| Finished | Oct 03 10:20:20 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292220324 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2292220324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/196.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.4177538857 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 74332520158 ps |
| CPU time | 156.62 seconds |
| Started | Oct 03 10:16:06 AM UTC 24 |
| Finished | Oct 03 10:18:45 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177538857 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4177538857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/197.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.3641285392 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 147695858437 ps |
| CPU time | 77.97 seconds |
| Started | Oct 03 10:16:09 AM UTC 24 |
| Finished | Oct 03 10:17:28 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641285392 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3641285392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/198.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.1188027601 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 345725174627 ps |
| CPU time | 692 seconds |
| Started | Oct 03 10:16:09 AM UTC 24 |
| Finished | Oct 03 10:27:50 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188027601 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1188027601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/199.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.1608761623 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11488067181 ps |
| CPU time | 32.19 seconds |
| Started | Oct 03 09:03:09 AM UTC 24 |
| Finished | Oct 03 09:03:43 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608761623 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.1608761623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.4222597318 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 205704920313 ps |
| CPU time | 91.27 seconds |
| Started | Oct 03 09:02:47 AM UTC 24 |
| Finished | Oct 03 09:04:20 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222597318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.4222597318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.481147480 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 18795421254 ps |
| CPU time | 15.22 seconds |
| Started | Oct 03 09:03:44 AM UTC 24 |
| Finished | Oct 03 09:04:01 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481147480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.481147480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.4288898334 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 347794504 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 09:04:08 AM UTC 24 |
| Finished | Oct 03 09:04:10 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288898334 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.4288898334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.291351515 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 34263222 ps |
| CPU time | 0.78 seconds |
| Started | Oct 03 09:04:05 AM UTC 24 |
| Finished | Oct 03 09:04:07 AM UTC 24 |
| Peak memory | 199484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291351515 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.291351515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/2.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.1355657135 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 502476498606 ps |
| CPU time | 299.26 seconds |
| Started | Oct 03 09:35:21 AM UTC 24 |
| Finished | Oct 03 09:40:24 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355657135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1355657135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/20.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.171927524 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 277350648164 ps |
| CPU time | 223.49 seconds |
| Started | Oct 03 09:35:11 AM UTC 24 |
| Finished | Oct 03 09:38:58 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171927524 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.171927524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/20.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.1224887606 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 31709115566 ps |
| CPU time | 297.55 seconds |
| Started | Oct 03 09:35:31 AM UTC 24 |
| Finished | Oct 03 09:40:33 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224887606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1224887606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/20.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all_with_rand_reset.923559792 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6800995584 ps |
| CPU time | 17.41 seconds |
| Started | Oct 03 09:35:33 AM UTC 24 |
| Finished | Oct 03 09:35:51 AM UTC 24 |
| Peak memory | 205624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=923559792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.923559792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/20.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.282930861 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 61821325453 ps |
| CPU time | 168.91 seconds |
| Started | Oct 03 09:36:06 AM UTC 24 |
| Finished | Oct 03 09:38:58 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282930861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.282930861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/21.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.2862344635 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 63787962263 ps |
| CPU time | 506.45 seconds |
| Started | Oct 03 09:35:52 AM UTC 24 |
| Finished | Oct 03 09:44:25 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862344635 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2862344635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/21.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.158635114 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 101707156309 ps |
| CPU time | 168.36 seconds |
| Started | Oct 03 09:36:20 AM UTC 24 |
| Finished | Oct 03 09:39:12 AM UTC 24 |
| Peak memory | 201088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158635114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.158635114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/21.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.1483300877 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 387684887384 ps |
| CPU time | 543.32 seconds |
| Started | Oct 03 09:36:28 AM UTC 24 |
| Finished | Oct 03 09:45:38 AM UTC 24 |
| Peak memory | 201212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483300877 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.1483300877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/21.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.1323197391 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 19468820076 ps |
| CPU time | 19.39 seconds |
| Started | Oct 03 09:36:40 AM UTC 24 |
| Finished | Oct 03 09:37:01 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323197391 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.1323197391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.2680664909 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 65529384239 ps |
| CPU time | 37.17 seconds |
| Started | Oct 03 09:36:36 AM UTC 24 |
| Finished | Oct 03 09:37:15 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680664909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2680664909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/22.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.2863872336 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 162901658328 ps |
| CPU time | 341.48 seconds |
| Started | Oct 03 09:36:33 AM UTC 24 |
| Finished | Oct 03 09:42:19 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863872336 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2863872336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/22.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.4285391909 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 54710609305 ps |
| CPU time | 66.99 seconds |
| Started | Oct 03 09:36:45 AM UTC 24 |
| Finished | Oct 03 09:37:54 AM UTC 24 |
| Peak memory | 201284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285391909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4285391909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/22.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.2560195100 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 198182134082 ps |
| CPU time | 214.76 seconds |
| Started | Oct 03 09:37:01 AM UTC 24 |
| Finished | Oct 03 09:40:40 AM UTC 24 |
| Peak memory | 201208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560195100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2560195100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/23.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.2660253895 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 35194373983 ps |
| CPU time | 81.08 seconds |
| Started | Oct 03 09:36:59 AM UTC 24 |
| Finished | Oct 03 09:38:23 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660253895 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2660253895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/23.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.3171430865 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 175634317669 ps |
| CPU time | 391.1 seconds |
| Started | Oct 03 09:37:02 AM UTC 24 |
| Finished | Oct 03 09:43:39 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171430865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3171430865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/23.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.912240142 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 21953820767 ps |
| CPU time | 59.9 seconds |
| Started | Oct 03 09:37:10 AM UTC 24 |
| Finished | Oct 03 09:38:11 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912240142 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.912240142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/23.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.2840188170 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 29459793749 ps |
| CPU time | 99.1 seconds |
| Started | Oct 03 09:37:31 AM UTC 24 |
| Finished | Oct 03 09:39:12 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840188170 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.2840188170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.1494930853 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 28879274950 ps |
| CPU time | 86.8 seconds |
| Started | Oct 03 09:37:29 AM UTC 24 |
| Finished | Oct 03 09:38:58 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494930853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1494930853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/24.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.136084225 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 96742372021 ps |
| CPU time | 91 seconds |
| Started | Oct 03 09:37:37 AM UTC 24 |
| Finished | Oct 03 09:39:10 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136084225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.136084225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/24.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.3259062109 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 97792974643 ps |
| CPU time | 272.96 seconds |
| Started | Oct 03 09:38:08 AM UTC 24 |
| Finished | Oct 03 09:42:44 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259062109 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.3259062109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.429184606 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 311158186207 ps |
| CPU time | 175.89 seconds |
| Started | Oct 03 09:38:03 AM UTC 24 |
| Finished | Oct 03 09:41:02 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429184606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.429184606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/25.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.2082870911 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 198102640412 ps |
| CPU time | 202.94 seconds |
| Started | Oct 03 09:37:55 AM UTC 24 |
| Finished | Oct 03 09:41:22 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082870911 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2082870911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/25.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.321918650 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 299904389798 ps |
| CPU time | 1843.48 seconds |
| Started | Oct 03 09:38:12 AM UTC 24 |
| Finished | Oct 03 10:09:16 AM UTC 24 |
| Peak memory | 202772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321918650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.321918650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/25.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.2087998170 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 3101832606 ps |
| CPU time | 7.95 seconds |
| Started | Oct 03 09:38:58 AM UTC 24 |
| Finished | Oct 03 09:39:07 AM UTC 24 |
| Peak memory | 201020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087998170 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.2087998170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.748931234 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 45925877104 ps |
| CPU time | 120.34 seconds |
| Started | Oct 03 09:38:51 AM UTC 24 |
| Finished | Oct 03 09:40:54 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748931234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.748931234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/26.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.3284389003 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 94721018431 ps |
| CPU time | 199.4 seconds |
| Started | Oct 03 09:38:24 AM UTC 24 |
| Finished | Oct 03 09:41:47 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284389003 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3284389003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/26.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.3378562372 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 41695946616 ps |
| CPU time | 106.05 seconds |
| Started | Oct 03 09:38:59 AM UTC 24 |
| Finished | Oct 03 09:40:48 AM UTC 24 |
| Peak memory | 201408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378562372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3378562372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/26.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.1276995004 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 9135214059 ps |
| CPU time | 31.05 seconds |
| Started | Oct 03 09:39:12 AM UTC 24 |
| Finished | Oct 03 09:39:44 AM UTC 24 |
| Peak memory | 201020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276995004 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.1276995004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.1049507049 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1743443710423 ps |
| CPU time | 2039.44 seconds |
| Started | Oct 03 09:39:09 AM UTC 24 |
| Finished | Oct 03 10:13:32 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049507049 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1049507049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/27.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.2170373079 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 404314271440 ps |
| CPU time | 217.74 seconds |
| Started | Oct 03 09:39:13 AM UTC 24 |
| Finished | Oct 03 09:42:55 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170373079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2170373079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/27.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.1511605661 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 491327404846 ps |
| CPU time | 321.65 seconds |
| Started | Oct 03 09:39:38 AM UTC 24 |
| Finished | Oct 03 09:45:04 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511605661 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.1511605661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.1914184102 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 125201798681 ps |
| CPU time | 145.97 seconds |
| Started | Oct 03 09:39:35 AM UTC 24 |
| Finished | Oct 03 09:42:04 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914184102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1914184102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/28.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.2407223263 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 160757833107 ps |
| CPU time | 338.92 seconds |
| Started | Oct 03 09:39:29 AM UTC 24 |
| Finished | Oct 03 09:45:12 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407223263 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2407223263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/28.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.1833515890 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 23103538914 ps |
| CPU time | 83.84 seconds |
| Started | Oct 03 09:39:45 AM UTC 24 |
| Finished | Oct 03 09:41:11 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833515890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1833515890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/28.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.2354326057 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 15429148855 ps |
| CPU time | 11.76 seconds |
| Started | Oct 03 09:40:34 AM UTC 24 |
| Finished | Oct 03 09:40:48 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354326057 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.2354326057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.1432245425 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 39801469654 ps |
| CPU time | 72.98 seconds |
| Started | Oct 03 09:40:25 AM UTC 24 |
| Finished | Oct 03 09:41:39 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432245425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1432245425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/29.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.3924360144 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 11762923825 ps |
| CPU time | 15.94 seconds |
| Started | Oct 03 09:40:40 AM UTC 24 |
| Finished | Oct 03 09:40:58 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924360144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3924360144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/29.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.2746097707 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 308916974130 ps |
| CPU time | 896.39 seconds |
| Started | Oct 03 09:40:45 AM UTC 24 |
| Finished | Oct 03 09:55:54 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746097707 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.2746097707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/29.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all_with_rand_reset.2169027555 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2375293730 ps |
| CPU time | 30.32 seconds |
| Started | Oct 03 09:40:41 AM UTC 24 |
| Finished | Oct 03 09:41:14 AM UTC 24 |
| Peak memory | 203236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2169027555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.rv_timer_stress_all_with_rand_reset.2169027555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/29.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.361264811 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 651479826024 ps |
| CPU time | 485.69 seconds |
| Started | Oct 03 09:04:30 AM UTC 24 |
| Finished | Oct 03 09:12:43 AM UTC 24 |
| Peak memory | 200984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361264811 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.361264811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.2982424594 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 123324387360 ps |
| CPU time | 293.45 seconds |
| Started | Oct 03 09:04:22 AM UTC 24 |
| Finished | Oct 03 09:09:21 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982424594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2982424594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.1913008319 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 43124685374 ps |
| CPU time | 36.55 seconds |
| Started | Oct 03 09:05:38 AM UTC 24 |
| Finished | Oct 03 09:06:16 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913008319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1913008319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.4166288055 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 138465624 ps |
| CPU time | 0.93 seconds |
| Started | Oct 03 09:07:31 AM UTC 24 |
| Finished | Oct 03 09:07:33 AM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166288055 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4166288055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.3576386386 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 207509117307 ps |
| CPU time | 103.33 seconds |
| Started | Oct 03 09:40:53 AM UTC 24 |
| Finished | Oct 03 09:42:39 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576386386 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.3576386386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.2382304520 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 63781131794 ps |
| CPU time | 61.06 seconds |
| Started | Oct 03 09:40:49 AM UTC 24 |
| Finished | Oct 03 09:41:52 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382304520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2382304520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/30.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.295106036 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 541935871383 ps |
| CPU time | 402.61 seconds |
| Started | Oct 03 09:40:49 AM UTC 24 |
| Finished | Oct 03 09:47:37 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295106036 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.295106036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/30.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.2375625690 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 874609012472 ps |
| CPU time | 1919.54 seconds |
| Started | Oct 03 09:40:54 AM UTC 24 |
| Finished | Oct 03 10:13:16 AM UTC 24 |
| Peak memory | 203032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375625690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2375625690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/30.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.2643199961 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 46342186871 ps |
| CPU time | 156.58 seconds |
| Started | Oct 03 09:41:12 AM UTC 24 |
| Finished | Oct 03 09:43:51 AM UTC 24 |
| Peak memory | 201408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643199961 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.2643199961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.234611591 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 280282222498 ps |
| CPU time | 112.41 seconds |
| Started | Oct 03 09:41:12 AM UTC 24 |
| Finished | Oct 03 09:43:06 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234611591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.234611591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/31.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.1873402927 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 182331293537 ps |
| CPU time | 217.17 seconds |
| Started | Oct 03 09:41:04 AM UTC 24 |
| Finished | Oct 03 09:44:44 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873402927 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1873402927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/31.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.1187339119 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 70495781405 ps |
| CPU time | 57.21 seconds |
| Started | Oct 03 09:41:15 AM UTC 24 |
| Finished | Oct 03 09:42:13 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187339119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1187339119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/31.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.2787163404 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 457743791413 ps |
| CPU time | 1234.37 seconds |
| Started | Oct 03 09:41:22 AM UTC 24 |
| Finished | Oct 03 10:02:10 AM UTC 24 |
| Peak memory | 203024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787163404 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.2787163404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/31.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.3893409813 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 30855295243 ps |
| CPU time | 79.01 seconds |
| Started | Oct 03 09:41:48 AM UTC 24 |
| Finished | Oct 03 09:43:09 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893409813 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.3893409813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.2323465670 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 363547778077 ps |
| CPU time | 199.66 seconds |
| Started | Oct 03 09:41:44 AM UTC 24 |
| Finished | Oct 03 09:45:07 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323465670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2323465670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/32.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.532332808 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 140863455278 ps |
| CPU time | 272.28 seconds |
| Started | Oct 03 09:41:40 AM UTC 24 |
| Finished | Oct 03 09:46:17 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532332808 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.532332808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/32.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.378888265 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 330414026031 ps |
| CPU time | 121.23 seconds |
| Started | Oct 03 09:41:48 AM UTC 24 |
| Finished | Oct 03 09:43:52 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378888265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.378888265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/32.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.371329051 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 7606051090530 ps |
| CPU time | 1888.86 seconds |
| Started | Oct 03 09:42:05 AM UTC 24 |
| Finished | Oct 03 10:13:55 AM UTC 24 |
| Peak memory | 202636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371329051 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.371329051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/32.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.3750628829 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 97074866237 ps |
| CPU time | 149.33 seconds |
| Started | Oct 03 09:42:17 AM UTC 24 |
| Finished | Oct 03 09:44:49 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750628829 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.3750628829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.1593245451 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 175404200075 ps |
| CPU time | 285.61 seconds |
| Started | Oct 03 09:42:14 AM UTC 24 |
| Finished | Oct 03 09:47:03 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593245451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1593245451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/33.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.1614169065 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 536828290539 ps |
| CPU time | 964.21 seconds |
| Started | Oct 03 09:42:09 AM UTC 24 |
| Finished | Oct 03 09:58:25 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614169065 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1614169065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/33.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.821914875 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 45947909748 ps |
| CPU time | 39.65 seconds |
| Started | Oct 03 09:42:19 AM UTC 24 |
| Finished | Oct 03 09:43:00 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821914875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.821914875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/33.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.346067491 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2462009379107 ps |
| CPU time | 887.36 seconds |
| Started | Oct 03 09:42:24 AM UTC 24 |
| Finished | Oct 03 09:57:22 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346067491 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.346067491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/33.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all_with_rand_reset.91706168 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3806669184 ps |
| CPU time | 41.41 seconds |
| Started | Oct 03 09:42:20 AM UTC 24 |
| Finished | Oct 03 09:43:03 AM UTC 24 |
| Peak memory | 205364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=91706168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.91706168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/33.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.285498021 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1182669743453 ps |
| CPU time | 610.66 seconds |
| Started | Oct 03 09:42:45 AM UTC 24 |
| Finished | Oct 03 09:53:03 AM UTC 24 |
| Peak memory | 201120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285498021 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.285498021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.618092279 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 15487230248 ps |
| CPU time | 33.08 seconds |
| Started | Oct 03 09:42:41 AM UTC 24 |
| Finished | Oct 03 09:43:16 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618092279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.618092279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/34.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.2280605844 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 159079888756 ps |
| CPU time | 457.75 seconds |
| Started | Oct 03 09:42:39 AM UTC 24 |
| Finished | Oct 03 09:50:23 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280605844 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2280605844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/34.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.121489724 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 29371942755 ps |
| CPU time | 48.71 seconds |
| Started | Oct 03 09:42:55 AM UTC 24 |
| Finished | Oct 03 09:43:46 AM UTC 24 |
| Peak memory | 200928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121489724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.121489724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/34.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.3219590894 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 778048022872 ps |
| CPU time | 861.77 seconds |
| Started | Oct 03 09:43:01 AM UTC 24 |
| Finished | Oct 03 09:57:32 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219590894 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.3219590894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/34.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.3830108042 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 143919670875 ps |
| CPU time | 147.18 seconds |
| Started | Oct 03 09:43:07 AM UTC 24 |
| Finished | Oct 03 09:45:37 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830108042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3830108042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/35.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.3914276745 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 580564667291 ps |
| CPU time | 538.9 seconds |
| Started | Oct 03 09:43:04 AM UTC 24 |
| Finished | Oct 03 09:52:10 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914276745 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3914276745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/35.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.4093220937 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 148598255251 ps |
| CPU time | 167.41 seconds |
| Started | Oct 03 09:43:10 AM UTC 24 |
| Finished | Oct 03 09:46:00 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093220937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4093220937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/35.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.1297157909 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 531681390297 ps |
| CPU time | 151.57 seconds |
| Started | Oct 03 09:43:36 AM UTC 24 |
| Finished | Oct 03 09:46:10 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297157909 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.1297157909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/35.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.3042852173 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 48218217813 ps |
| CPU time | 95.06 seconds |
| Started | Oct 03 09:43:47 AM UTC 24 |
| Finished | Oct 03 09:45:24 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042852173 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.3042852173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.2673583222 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 113454259285 ps |
| CPU time | 222.33 seconds |
| Started | Oct 03 09:43:40 AM UTC 24 |
| Finished | Oct 03 09:47:26 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673583222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2673583222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/36.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.1281533891 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 308157005335 ps |
| CPU time | 158.13 seconds |
| Started | Oct 03 09:43:39 AM UTC 24 |
| Finished | Oct 03 09:46:20 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281533891 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1281533891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/36.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.121724812 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 66662355 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 09:43:53 AM UTC 24 |
| Finished | Oct 03 09:43:55 AM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121724812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.121724812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/36.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.3773029984 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1700525107668 ps |
| CPU time | 754.41 seconds |
| Started | Oct 03 09:43:56 AM UTC 24 |
| Finished | Oct 03 09:56:39 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773029984 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.3773029984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/36.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.2591495055 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 32458417143 ps |
| CPU time | 28.02 seconds |
| Started | Oct 03 09:44:26 AM UTC 24 |
| Finished | Oct 03 09:44:55 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591495055 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.2591495055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.2156566582 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 272125517311 ps |
| CPU time | 130.2 seconds |
| Started | Oct 03 09:44:10 AM UTC 24 |
| Finished | Oct 03 09:46:22 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156566582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2156566582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/37.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.2687865359 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 59212897100 ps |
| CPU time | 343.07 seconds |
| Started | Oct 03 09:44:00 AM UTC 24 |
| Finished | Oct 03 09:49:48 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687865359 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2687865359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/37.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.2812022484 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 105099453662 ps |
| CPU time | 85.97 seconds |
| Started | Oct 03 09:44:45 AM UTC 24 |
| Finished | Oct 03 09:46:13 AM UTC 24 |
| Peak memory | 201408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812022484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2812022484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/37.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all_with_rand_reset.2710757140 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3795122505 ps |
| CPU time | 24.98 seconds |
| Started | Oct 03 09:44:49 AM UTC 24 |
| Finished | Oct 03 09:45:16 AM UTC 24 |
| Peak memory | 205360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2710757140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.rv_timer_stress_all_with_rand_reset.2710757140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/37.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.2820822251 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 93138403365 ps |
| CPU time | 79.29 seconds |
| Started | Oct 03 09:45:08 AM UTC 24 |
| Finished | Oct 03 09:46:29 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820822251 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.2820822251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.2347852648 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 101970327588 ps |
| CPU time | 249.1 seconds |
| Started | Oct 03 09:45:05 AM UTC 24 |
| Finished | Oct 03 09:49:18 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347852648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2347852648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/38.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.3159819872 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 518899516510 ps |
| CPU time | 1118.4 seconds |
| Started | Oct 03 09:44:57 AM UTC 24 |
| Finished | Oct 03 10:03:48 AM UTC 24 |
| Peak memory | 202772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159819872 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3159819872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/38.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.548159679 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 44046839379 ps |
| CPU time | 91.56 seconds |
| Started | Oct 03 09:45:13 AM UTC 24 |
| Finished | Oct 03 09:46:47 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548159679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.548159679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/38.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.4109737418 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 263094940467 ps |
| CPU time | 624.06 seconds |
| Started | Oct 03 09:45:25 AM UTC 24 |
| Finished | Oct 03 09:55:56 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109737418 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.4109737418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/38.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.3217540586 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1054393777105 ps |
| CPU time | 799.6 seconds |
| Started | Oct 03 09:45:39 AM UTC 24 |
| Finished | Oct 03 09:59:09 AM UTC 24 |
| Peak memory | 201000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217540586 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.3217540586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.1687428001 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 91275798486 ps |
| CPU time | 162.97 seconds |
| Started | Oct 03 09:45:37 AM UTC 24 |
| Finished | Oct 03 09:48:23 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687428001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1687428001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/39.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.811980257 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1456062050736 ps |
| CPU time | 543.31 seconds |
| Started | Oct 03 09:45:35 AM UTC 24 |
| Finished | Oct 03 09:54:46 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811980257 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.811980257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/39.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.2451048571 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 87418647697 ps |
| CPU time | 307.25 seconds |
| Started | Oct 03 09:46:01 AM UTC 24 |
| Finished | Oct 03 09:51:12 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451048571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2451048571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/39.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all_with_rand_reset.2721965960 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 5276385855 ps |
| CPU time | 70.48 seconds |
| Started | Oct 03 09:46:01 AM UTC 24 |
| Finished | Oct 03 09:47:13 AM UTC 24 |
| Peak memory | 205488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2721965960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.rv_timer_stress_all_with_rand_reset.2721965960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/39.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.3143535124 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1648442662640 ps |
| CPU time | 1196.08 seconds |
| Started | Oct 03 09:09:12 AM UTC 24 |
| Finished | Oct 03 09:29:25 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143535124 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.3143535124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.2229044814 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 104574969084 ps |
| CPU time | 225.09 seconds |
| Started | Oct 03 09:07:44 AM UTC 24 |
| Finished | Oct 03 09:11:33 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229044814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2229044814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.2964788402 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 75282742034 ps |
| CPU time | 93.91 seconds |
| Started | Oct 03 09:07:35 AM UTC 24 |
| Finished | Oct 03 09:09:11 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964788402 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2964788402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.4164796915 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 136350768 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 09:09:21 AM UTC 24 |
| Finished | Oct 03 09:09:23 AM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164796915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.4164796915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.529883797 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 69956814 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 09:11:05 AM UTC 24 |
| Finished | Oct 03 09:11:07 AM UTC 24 |
| Peak memory | 232592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529883797 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.529883797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.3686595106 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1703133256688 ps |
| CPU time | 1314.97 seconds |
| Started | Oct 03 09:09:48 AM UTC 24 |
| Finished | Oct 03 09:32:02 AM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686595106 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.3686595106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/4.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.273910194 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 799215387927 ps |
| CPU time | 872.74 seconds |
| Started | Oct 03 09:46:21 AM UTC 24 |
| Finished | Oct 03 10:01:04 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273910194 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.273910194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.1031860652 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 99393161162 ps |
| CPU time | 161.65 seconds |
| Started | Oct 03 09:46:17 AM UTC 24 |
| Finished | Oct 03 09:49:02 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031860652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1031860652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/40.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.731630361 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 283909756901 ps |
| CPU time | 799.7 seconds |
| Started | Oct 03 09:46:14 AM UTC 24 |
| Finished | Oct 03 09:59:44 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731630361 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.731630361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/40.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.1263992099 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 24222576523 ps |
| CPU time | 26.06 seconds |
| Started | Oct 03 09:46:23 AM UTC 24 |
| Finished | Oct 03 09:46:52 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263992099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1263992099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/40.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all_with_rand_reset.1639522025 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1929175405 ps |
| CPU time | 31.42 seconds |
| Started | Oct 03 09:46:30 AM UTC 24 |
| Finished | Oct 03 09:47:02 AM UTC 24 |
| Peak memory | 203176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1639522025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.rv_timer_stress_all_with_rand_reset.1639522025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/40.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.3257059559 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 295829801141 ps |
| CPU time | 278.73 seconds |
| Started | Oct 03 09:47:03 AM UTC 24 |
| Finished | Oct 03 09:51:46 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257059559 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.3257059559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.3093898660 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 194758748499 ps |
| CPU time | 73.49 seconds |
| Started | Oct 03 09:46:53 AM UTC 24 |
| Finished | Oct 03 09:48:08 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093898660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3093898660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/41.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.553650463 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1687697825276 ps |
| CPU time | 2329.95 seconds |
| Started | Oct 03 09:46:49 AM UTC 24 |
| Finished | Oct 03 10:26:07 AM UTC 24 |
| Peak memory | 202896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553650463 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.553650463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/41.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.1956243737 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 55648526 ps |
| CPU time | 0.82 seconds |
| Started | Oct 03 09:47:04 AM UTC 24 |
| Finished | Oct 03 09:47:06 AM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956243737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1956243737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/41.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.2876444464 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 499248716175 ps |
| CPU time | 298.77 seconds |
| Started | Oct 03 09:47:10 AM UTC 24 |
| Finished | Oct 03 09:52:13 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876444464 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.2876444464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/41.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.763034951 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 21951928534 ps |
| CPU time | 15.32 seconds |
| Started | Oct 03 09:47:28 AM UTC 24 |
| Finished | Oct 03 09:47:45 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763034951 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.763034951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.363706414 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 176912380967 ps |
| CPU time | 129.89 seconds |
| Started | Oct 03 09:47:21 AM UTC 24 |
| Finished | Oct 03 09:49:33 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363706414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.363706414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/42.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.2026798724 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 38976604943 ps |
| CPU time | 56.64 seconds |
| Started | Oct 03 09:47:38 AM UTC 24 |
| Finished | Oct 03 09:48:37 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026798724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2026798724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/42.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all_with_rand_reset.1822574507 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2807810670 ps |
| CPU time | 31.74 seconds |
| Started | Oct 03 09:47:47 AM UTC 24 |
| Finished | Oct 03 09:48:20 AM UTC 24 |
| Peak memory | 205360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1822574507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.rv_timer_stress_all_with_rand_reset.1822574507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/42.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.3180620899 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 290503767503 ps |
| CPU time | 360.12 seconds |
| Started | Oct 03 09:48:37 AM UTC 24 |
| Finished | Oct 03 09:54:42 AM UTC 24 |
| Peak memory | 201260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180620899 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.3180620899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.1208431004 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 30598803584 ps |
| CPU time | 46.25 seconds |
| Started | Oct 03 09:48:25 AM UTC 24 |
| Finished | Oct 03 09:49:13 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208431004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1208431004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/43.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.3279677435 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 224691432783 ps |
| CPU time | 136.82 seconds |
| Started | Oct 03 09:48:21 AM UTC 24 |
| Finished | Oct 03 09:50:40 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279677435 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3279677435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/43.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.3474819248 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 350490461122 ps |
| CPU time | 233.33 seconds |
| Started | Oct 03 09:48:49 AM UTC 24 |
| Finished | Oct 03 09:52:47 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474819248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3474819248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/43.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.2336198724 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 39789792 ps |
| CPU time | 0.95 seconds |
| Started | Oct 03 09:49:02 AM UTC 24 |
| Finished | Oct 03 09:49:04 AM UTC 24 |
| Peak memory | 199488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336198724 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.2336198724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/43.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.1734921427 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 110851474294 ps |
| CPU time | 169.38 seconds |
| Started | Oct 03 09:49:19 AM UTC 24 |
| Finished | Oct 03 09:52:11 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734921427 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.1734921427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.887171140 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 750758538790 ps |
| CPU time | 320.09 seconds |
| Started | Oct 03 09:49:14 AM UTC 24 |
| Finished | Oct 03 09:54:38 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887171140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.887171140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/44.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.1747090451 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 203866183084 ps |
| CPU time | 169.7 seconds |
| Started | Oct 03 09:49:05 AM UTC 24 |
| Finished | Oct 03 09:51:58 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747090451 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1747090451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/44.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.2348630479 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 27398144048 ps |
| CPU time | 82 seconds |
| Started | Oct 03 09:49:21 AM UTC 24 |
| Finished | Oct 03 09:50:45 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348630479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2348630479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/44.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.565803155 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 830872884087 ps |
| CPU time | 2059.75 seconds |
| Started | Oct 03 09:49:48 AM UTC 24 |
| Finished | Oct 03 10:24:31 AM UTC 24 |
| Peak memory | 202640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565803155 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.565803155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/44.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all_with_rand_reset.653652838 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1280511587 ps |
| CPU time | 18.63 seconds |
| Started | Oct 03 09:49:34 AM UTC 24 |
| Finished | Oct 03 09:49:54 AM UTC 24 |
| Peak memory | 203196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=653652838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.653652838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/44.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.796799849 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1559911527407 ps |
| CPU time | 534.57 seconds |
| Started | Oct 03 09:50:23 AM UTC 24 |
| Finished | Oct 03 09:59:25 AM UTC 24 |
| Peak memory | 200984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796799849 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.796799849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.3245441372 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 387273710884 ps |
| CPU time | 154.47 seconds |
| Started | Oct 03 09:50:14 AM UTC 24 |
| Finished | Oct 03 09:52:51 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245441372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3245441372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/45.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.1722472018 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1489336341567 ps |
| CPU time | 945.48 seconds |
| Started | Oct 03 09:49:55 AM UTC 24 |
| Finished | Oct 03 10:05:52 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722472018 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1722472018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/45.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.1735068194 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 262937549571 ps |
| CPU time | 191.39 seconds |
| Started | Oct 03 09:50:39 AM UTC 24 |
| Finished | Oct 03 09:53:54 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735068194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1735068194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/45.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.3258456333 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 130714095478 ps |
| CPU time | 429.05 seconds |
| Started | Oct 03 09:50:44 AM UTC 24 |
| Finished | Oct 03 09:57:59 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258456333 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.3258456333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/45.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all_with_rand_reset.4255199690 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3767862543 ps |
| CPU time | 20.54 seconds |
| Started | Oct 03 09:50:41 AM UTC 24 |
| Finished | Oct 03 09:51:02 AM UTC 24 |
| Peak memory | 203240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4255199690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.rv_timer_stress_all_with_rand_reset.4255199690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/45.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.163357680 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 101887988309 ps |
| CPU time | 50.08 seconds |
| Started | Oct 03 09:50:47 AM UTC 24 |
| Finished | Oct 03 09:51:38 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163357680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.163357680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/46.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.3090514282 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 91038706051 ps |
| CPU time | 304.92 seconds |
| Started | Oct 03 09:50:46 AM UTC 24 |
| Finished | Oct 03 09:55:55 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090514282 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3090514282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/46.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.906893525 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 752066982 ps |
| CPU time | 4.41 seconds |
| Started | Oct 03 09:51:03 AM UTC 24 |
| Finished | Oct 03 09:51:09 AM UTC 24 |
| Peak memory | 200948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906893525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.906893525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/46.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.1411946709 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 381371975533 ps |
| CPU time | 1180.82 seconds |
| Started | Oct 03 09:51:13 AM UTC 24 |
| Finished | Oct 03 10:11:07 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411946709 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.1411946709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/46.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.3858325605 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 412322970773 ps |
| CPU time | 865.91 seconds |
| Started | Oct 03 09:51:47 AM UTC 24 |
| Finished | Oct 03 10:06:23 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858325605 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.3858325605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.2777258893 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 66868821461 ps |
| CPU time | 116.24 seconds |
| Started | Oct 03 09:51:40 AM UTC 24 |
| Finished | Oct 03 09:53:38 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777258893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2777258893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/47.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.3358497173 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 120623965777 ps |
| CPU time | 1482.3 seconds |
| Started | Oct 03 09:51:14 AM UTC 24 |
| Finished | Oct 03 10:16:15 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358497173 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3358497173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/47.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.4228218123 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 55722626 ps |
| CPU time | 0.83 seconds |
| Started | Oct 03 09:51:59 AM UTC 24 |
| Finished | Oct 03 09:52:01 AM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228218123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.4228218123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/47.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.1729998289 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 45333180 ps |
| CPU time | 0.93 seconds |
| Started | Oct 03 09:52:06 AM UTC 24 |
| Finished | Oct 03 09:52:08 AM UTC 24 |
| Peak memory | 199684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729998289 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.1729998289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/47.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.2664949435 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 23410545701 ps |
| CPU time | 70.19 seconds |
| Started | Oct 03 09:52:12 AM UTC 24 |
| Finished | Oct 03 09:53:24 AM UTC 24 |
| Peak memory | 201260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664949435 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.2664949435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.2568210296 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 562169390820 ps |
| CPU time | 772.85 seconds |
| Started | Oct 03 09:52:09 AM UTC 24 |
| Finished | Oct 03 10:05:11 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568210296 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2568210296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/48.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.3505566707 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 21439212422 ps |
| CPU time | 97.44 seconds |
| Started | Oct 03 09:52:14 AM UTC 24 |
| Finished | Oct 03 09:53:54 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505566707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3505566707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/48.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.3267554556 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 625000023399 ps |
| CPU time | 2523.77 seconds |
| Started | Oct 03 09:52:33 AM UTC 24 |
| Finished | Oct 03 10:35:06 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267554556 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.3267554556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/48.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.1910194887 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1643205978036 ps |
| CPU time | 917.48 seconds |
| Started | Oct 03 09:52:53 AM UTC 24 |
| Finished | Oct 03 10:08:21 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910194887 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.1910194887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.3307390340 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 772776542563 ps |
| CPU time | 433.76 seconds |
| Started | Oct 03 09:52:49 AM UTC 24 |
| Finished | Oct 03 10:00:09 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307390340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3307390340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/49.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.3611582349 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 12897289718 ps |
| CPU time | 172.81 seconds |
| Started | Oct 03 09:52:48 AM UTC 24 |
| Finished | Oct 03 09:55:43 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611582349 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3611582349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/49.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.1004808602 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 38574027756 ps |
| CPU time | 124.24 seconds |
| Started | Oct 03 09:52:53 AM UTC 24 |
| Finished | Oct 03 09:54:59 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004808602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1004808602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/49.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.514927159 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 19861908069 ps |
| CPU time | 51.47 seconds |
| Started | Oct 03 09:12:44 AM UTC 24 |
| Finished | Oct 03 09:13:37 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514927159 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.514927159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.3391243725 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 84356816590 ps |
| CPU time | 167.89 seconds |
| Started | Oct 03 09:11:33 AM UTC 24 |
| Finished | Oct 03 09:14:25 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391243725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3391243725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.1203363389 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 446224006046 ps |
| CPU time | 1352.15 seconds |
| Started | Oct 03 09:11:08 AM UTC 24 |
| Finished | Oct 03 09:34:01 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203363389 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1203363389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.1975683514 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 63637421789 ps |
| CPU time | 148.03 seconds |
| Started | Oct 03 09:13:30 AM UTC 24 |
| Finished | Oct 03 09:16:01 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975683514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1975683514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.1500170590 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 84449611252 ps |
| CPU time | 171.98 seconds |
| Started | Oct 03 09:14:20 AM UTC 24 |
| Finished | Oct 03 09:17:15 AM UTC 24 |
| Peak memory | 201088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500170590 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.1500170590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all_with_rand_reset.2884360339 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3653480264 ps |
| CPU time | 38.74 seconds |
| Started | Oct 03 09:13:38 AM UTC 24 |
| Finished | Oct 03 09:14:19 AM UTC 24 |
| Peak memory | 205556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2884360339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.rv_timer_stress_all_with_rand_reset.2884360339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.100871261 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 19709026291 ps |
| CPU time | 254.17 seconds |
| Started | Oct 03 09:53:39 AM UTC 24 |
| Finished | Oct 03 09:57:57 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100871261 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.100871261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/50.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.2030805713 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 222685971608 ps |
| CPU time | 153.25 seconds |
| Started | Oct 03 09:53:43 AM UTC 24 |
| Finished | Oct 03 09:56:19 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030805713 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2030805713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/51.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.2418835812 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 34587118248 ps |
| CPU time | 44.79 seconds |
| Started | Oct 03 09:53:55 AM UTC 24 |
| Finished | Oct 03 09:54:41 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418835812 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2418835812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/53.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.922207014 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 125295283212 ps |
| CPU time | 459.2 seconds |
| Started | Oct 03 09:54:32 AM UTC 24 |
| Finished | Oct 03 10:02:17 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922207014 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.922207014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/54.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.1440270369 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 35932117529 ps |
| CPU time | 221 seconds |
| Started | Oct 03 09:54:39 AM UTC 24 |
| Finished | Oct 03 09:58:24 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440270369 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1440270369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/55.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.2256834154 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 197896721225 ps |
| CPU time | 938.13 seconds |
| Started | Oct 03 09:54:42 AM UTC 24 |
| Finished | Oct 03 10:10:31 AM UTC 24 |
| Peak memory | 202960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256834154 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2256834154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/56.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.3159832285 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 444639127834 ps |
| CPU time | 214.97 seconds |
| Started | Oct 03 09:54:43 AM UTC 24 |
| Finished | Oct 03 09:58:22 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159832285 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3159832285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/57.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.1606246994 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 48644680062 ps |
| CPU time | 74.43 seconds |
| Started | Oct 03 09:54:43 AM UTC 24 |
| Finished | Oct 03 09:55:59 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606246994 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1606246994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/58.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.2439931239 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 133360345748 ps |
| CPU time | 270.19 seconds |
| Started | Oct 03 09:54:46 AM UTC 24 |
| Finished | Oct 03 09:59:20 AM UTC 24 |
| Peak memory | 201208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439931239 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2439931239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/59.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.2983533662 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 527413993202 ps |
| CPU time | 297.11 seconds |
| Started | Oct 03 09:17:04 AM UTC 24 |
| Finished | Oct 03 09:22:07 AM UTC 24 |
| Peak memory | 201248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983533662 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.2983533662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.2344929287 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 29179573065 ps |
| CPU time | 59.98 seconds |
| Started | Oct 03 09:16:01 AM UTC 24 |
| Finished | Oct 03 09:17:03 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344929287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2344929287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/6.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.1521364181 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 111942050942 ps |
| CPU time | 1151.19 seconds |
| Started | Oct 03 09:17:16 AM UTC 24 |
| Finished | Oct 03 09:36:44 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521364181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1521364181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/6.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.3220064363 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 364997555163 ps |
| CPU time | 243.06 seconds |
| Started | Oct 03 09:21:46 AM UTC 24 |
| Finished | Oct 03 09:25:54 AM UTC 24 |
| Peak memory | 201280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220064363 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.3220064363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/6.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.441812039 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 34642344155 ps |
| CPU time | 82.21 seconds |
| Started | Oct 03 09:54:46 AM UTC 24 |
| Finished | Oct 03 09:56:11 AM UTC 24 |
| Peak memory | 200932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441812039 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.441812039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/60.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.1369069199 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 105903647381 ps |
| CPU time | 879.18 seconds |
| Started | Oct 03 09:55:00 AM UTC 24 |
| Finished | Oct 03 10:09:50 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369069199 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1369069199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/62.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.556520384 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 90446910402 ps |
| CPU time | 213.03 seconds |
| Started | Oct 03 09:55:46 AM UTC 24 |
| Finished | Oct 03 09:59:22 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556520384 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.556520384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/64.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.2034454229 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 200703283424 ps |
| CPU time | 281.22 seconds |
| Started | Oct 03 09:55:57 AM UTC 24 |
| Finished | Oct 03 10:00:43 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034454229 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2034454229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/67.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.4030412602 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 42904906200 ps |
| CPU time | 82.88 seconds |
| Started | Oct 03 09:56:11 AM UTC 24 |
| Finished | Oct 03 09:57:36 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030412602 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.4030412602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/69.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.4168661767 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 487934939091 ps |
| CPU time | 553.91 seconds |
| Started | Oct 03 09:27:38 AM UTC 24 |
| Finished | Oct 03 09:37:01 AM UTC 24 |
| Peak memory | 202764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168661767 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.4168661767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.241412797 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 172393263781 ps |
| CPU time | 100.04 seconds |
| Started | Oct 03 09:25:55 AM UTC 24 |
| Finished | Oct 03 09:27:37 AM UTC 24 |
| Peak memory | 201408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241412797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.241412797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.1367613290 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 243505979218 ps |
| CPU time | 612.55 seconds |
| Started | Oct 03 09:22:07 AM UTC 24 |
| Finished | Oct 03 09:32:30 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367613290 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1367613290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.4001425524 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 890203075 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 09:27:40 AM UTC 24 |
| Finished | Oct 03 09:27:43 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001425524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.4001425524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all_with_rand_reset.3200431919 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2651163592 ps |
| CPU time | 35.5 seconds |
| Started | Oct 03 09:27:44 AM UTC 24 |
| Finished | Oct 03 09:28:22 AM UTC 24 |
| Peak memory | 205560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3200431919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.rv_timer_stress_all_with_rand_reset.3200431919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/7.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.3819995005 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 418135974684 ps |
| CPU time | 579.82 seconds |
| Started | Oct 03 09:56:20 AM UTC 24 |
| Finished | Oct 03 10:06:08 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819995005 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3819995005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/70.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.1806113422 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 50089740221 ps |
| CPU time | 149.14 seconds |
| Started | Oct 03 09:56:23 AM UTC 24 |
| Finished | Oct 03 09:58:55 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806113422 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1806113422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/71.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.2960956834 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 331860156 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 09:56:40 AM UTC 24 |
| Finished | Oct 03 09:56:42 AM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960956834 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2960956834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/72.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.3363658174 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 93656075260 ps |
| CPU time | 239.13 seconds |
| Started | Oct 03 09:56:43 AM UTC 24 |
| Finished | Oct 03 10:00:45 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363658174 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3363658174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/73.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.3825592167 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 292009168643 ps |
| CPU time | 385.81 seconds |
| Started | Oct 03 09:57:23 AM UTC 24 |
| Finished | Oct 03 10:03:54 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825592167 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3825592167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/74.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.1687535560 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 656321552896 ps |
| CPU time | 505.52 seconds |
| Started | Oct 03 09:57:33 AM UTC 24 |
| Finished | Oct 03 10:06:05 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687535560 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1687535560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/75.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.258662698 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 710832103349 ps |
| CPU time | 508.42 seconds |
| Started | Oct 03 09:32:03 AM UTC 24 |
| Finished | Oct 03 09:40:38 AM UTC 24 |
| Peak memory | 202700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258662698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.258662698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/8.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.164163039 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 36378088949 ps |
| CPU time | 222.77 seconds |
| Started | Oct 03 09:34:00 AM UTC 24 |
| Finished | Oct 03 09:37:47 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164163039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.164163039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/8.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.3942999454 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 206325808426 ps |
| CPU time | 96.13 seconds |
| Started | Oct 03 09:58:14 AM UTC 24 |
| Finished | Oct 03 09:59:52 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942999454 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3942999454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/80.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.3822719682 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 890037812570 ps |
| CPU time | 978.07 seconds |
| Started | Oct 03 09:58:23 AM UTC 24 |
| Finished | Oct 03 10:14:52 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822719682 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3822719682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/81.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.3106734183 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 38084898509 ps |
| CPU time | 32.13 seconds |
| Started | Oct 03 09:58:26 AM UTC 24 |
| Finished | Oct 03 09:58:59 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106734183 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3106734183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/83.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.980181059 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 91907131921 ps |
| CPU time | 151.11 seconds |
| Started | Oct 03 09:58:56 AM UTC 24 |
| Finished | Oct 03 10:01:30 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980181059 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.980181059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/84.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.3518928641 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 79363299145 ps |
| CPU time | 130.15 seconds |
| Started | Oct 03 09:59:00 AM UTC 24 |
| Finished | Oct 03 10:01:13 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518928641 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3518928641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/85.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.109940496 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 499059765698 ps |
| CPU time | 415.33 seconds |
| Started | Oct 03 09:59:09 AM UTC 24 |
| Finished | Oct 03 10:06:10 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109940496 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.109940496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/86.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.3162884940 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 266051879295 ps |
| CPU time | 226.78 seconds |
| Started | Oct 03 09:59:21 AM UTC 24 |
| Finished | Oct 03 10:03:12 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162884940 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3162884940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/87.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.2454183834 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 200884702039 ps |
| CPU time | 127.22 seconds |
| Started | Oct 03 09:59:23 AM UTC 24 |
| Finished | Oct 03 10:01:33 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454183834 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2454183834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/88.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.346441672 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 284184408126 ps |
| CPU time | 371.39 seconds |
| Started | Oct 03 09:59:25 AM UTC 24 |
| Finished | Oct 03 10:05:42 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346441672 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.346441672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/89.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.526491819 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 672264555475 ps |
| CPU time | 1699.5 seconds |
| Started | Oct 03 09:34:03 AM UTC 24 |
| Finished | Oct 03 10:02:43 AM UTC 24 |
| Peak memory | 202608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526491819 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.526491819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.2021188422 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 234228908104 ps |
| CPU time | 455.13 seconds |
| Started | Oct 03 09:34:03 AM UTC 24 |
| Finished | Oct 03 09:41:44 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021188422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2021188422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/9.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.2788535125 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 386824064013 ps |
| CPU time | 247.87 seconds |
| Started | Oct 03 09:34:02 AM UTC 24 |
| Finished | Oct 03 09:38:13 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788535125 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2788535125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/9.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.2939699435 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 414159667933 ps |
| CPU time | 149.82 seconds |
| Started | Oct 03 09:34:03 AM UTC 24 |
| Finished | Oct 03 09:36:35 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939699435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2939699435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/9.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.2477915764 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 128938607945 ps |
| CPU time | 436.51 seconds |
| Started | Oct 03 09:59:44 AM UTC 24 |
| Finished | Oct 03 10:07:07 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477915764 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2477915764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/90.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.943576510 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 679022924428 ps |
| CPU time | 259.93 seconds |
| Started | Oct 03 10:00:10 AM UTC 24 |
| Finished | Oct 03 10:04:33 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943576510 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.943576510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/92.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.2825887222 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 216133561150 ps |
| CPU time | 421.06 seconds |
| Started | Oct 03 10:00:44 AM UTC 24 |
| Finished | Oct 03 10:07:51 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825887222 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2825887222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/93.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.1266954673 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 27841745223 ps |
| CPU time | 192.74 seconds |
| Started | Oct 03 10:00:47 AM UTC 24 |
| Finished | Oct 03 10:04:03 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266954673 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1266954673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/94.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.1707308973 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 628158591694 ps |
| CPU time | 344.7 seconds |
| Started | Oct 03 10:00:57 AM UTC 24 |
| Finished | Oct 03 10:06:47 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707308973 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1707308973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/95.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.61396460 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 245784558245 ps |
| CPU time | 236.82 seconds |
| Started | Oct 03 10:01:05 AM UTC 24 |
| Finished | Oct 03 10:05:06 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61396460 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.61396460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/96.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.2744237733 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 76034978562 ps |
| CPU time | 106.43 seconds |
| Started | Oct 03 10:01:13 AM UTC 24 |
| Finished | Oct 03 10:03:02 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744237733 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2744237733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/97.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.2240199339 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 135877988880 ps |
| CPU time | 678.03 seconds |
| Started | Oct 03 10:01:30 AM UTC 24 |
| Finished | Oct 03 10:12:57 AM UTC 24 |
| Peak memory | 202768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240199339 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2240199339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rv_timer-sim-vcs/99.rv_timer_random/latest |
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