Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71889643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

71998304

1

T1

1568

T2

1

T3

659

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143765074	1			T1	3193		T2	1		T3	1289
values[0x0]	59362	1			T1	11		T3	17		T4	40
values[0x1]	63511	1			T1	9		T3	11		T4	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57447419	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

86440528

1

T1

1899

T2

1

T3

787

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	509177	1			T10	95		T19	3		T24	12
valid_sources[0x01]	419585	1			T10	94		T19	7		T24	5
valid_sources[0x02]	1540966	1			T10	109		T19	7		T24	13
valid_sources[0x03]	429305	1			T4	4		T10	80		T19	6
valid_sources[0x04]	426587	1			T10	80		T19	2		T24	6
valid_sources[0x05]	427931	1			T10	61		T19	5		T24	7
valid_sources[0x06]	426628	1			T4	10		T10	76		T19	6
valid_sources[0x07]	422499	1			T10	71		T19	4		T24	10
valid_sources[0x08]	1149887	1			T10	126		T19	4		T24	11
valid_sources[0x09]	433397	1			T9	1		T10	60		T19	12
valid_sources[0x0a]	420701	1			T10	60		T19	3		T24	8
valid_sources[0x0b]	423688	1			T10	102		T19	5		T24	8
valid_sources[0x0c]	424148	1			T7	5		T10	82		T19	4
valid_sources[0x0d]	498708	1			T10	54		T19	12		T24	8
valid_sources[0x0e]	421937	1			T10	101		T19	11		T24	9
valid_sources[0x0f]	423738	1			T4	4		T7	1		T10	81
valid_sources[0x10]	423829	1			T10	101		T19	7		T24	5
valid_sources[0x11]	424171	1			T7	1		T10	100		T19	4
valid_sources[0x12]	425416	1			T4	3		T10	84		T19	7
valid_sources[0x13]	485380	1			T10	133		T19	12		T24	6
valid_sources[0x14]	428142	1			T7	1		T9	1		T10	80
valid_sources[0x15]	847946	1			T9	2		T10	61		T19	15
valid_sources[0x16]	1914123	1			T7	1		T10	119		T19	5
valid_sources[0x17]	423037	1			T10	51		T19	4		T24	6
valid_sources[0x18]	429371	1			T4	2		T10	65		T19	7
valid_sources[0x19]	427298	1			T10	101		T19	12		T24	2
valid_sources[0x1a]	427053	1			T4	5		T10	86		T19	13
valid_sources[0x1b]	425658	1			T7	1		T10	68		T19	7
valid_sources[0x1c]	426409	1			T10	81		T19	11		T24	8
valid_sources[0x1d]	425632	1			T1	3213		T10	57		T19	10
valid_sources[0x1e]	423413	1			T10	103		T19	5		T24	6
valid_sources[0x1f]	420229	1			T4	1		T10	97		T19	11
valid_sources[0x20]	421457	1			T9	2		T10	74		T19	15
valid_sources[0x21]	422657	1			T10	81		T19	5		T24	8
valid_sources[0x22]	426964	1			T4	7		T7	2		T10	60
valid_sources[0x23]	685754	1			T10	87		T19	6		T24	8
valid_sources[0x24]	422586	1			T10	105		T19	10		T24	4
valid_sources[0x25]	424646	1			T4	1		T10	75		T19	6
valid_sources[0x26]	422070	1			T7	2		T10	54		T19	5
valid_sources[0x27]	428790	1			T7	5		T9	1		T10	65
valid_sources[0x28]	422116	1			T10	70		T19	7		T24	3
valid_sources[0x29]	421389	1			T10	65		T19	9		T24	5
valid_sources[0x2a]	439535	1			T10	84		T19	13		T24	4
valid_sources[0x2b]	455610	1			T10	44		T19	7		T24	13
valid_sources[0x2c]	422748	1			T10	112		T19	9		T24	7
valid_sources[0x2d]	425408	1			T4	5		T7	13		T10	65
valid_sources[0x2e]	424034	1			T4	2		T10	86		T19	12
valid_sources[0x2f]	448420	1			T10	116		T19	10		T24	6
valid_sources[0x30]	427228	1			T7	5		T10	73		T19	18
valid_sources[0x31]	541364	1			T10	73		T19	7		T24	4
valid_sources[0x32]	471758	1			T4	7		T8	1		T9	3
valid_sources[0x33]	420963	1			T10	62		T19	4		T24	7
valid_sources[0x34]	420220	1			T4	1		T10	65		T19	3
valid_sources[0x35]	437055	1			T10	88		T19	6		T24	6
valid_sources[0x36]	423149	1			T10	90		T19	3		T24	10
valid_sources[0x37]	1184893	1			T10	57		T19	4		T24	8
valid_sources[0x38]	423812	1			T10	70		T19	11		T24	13
valid_sources[0x39]	431104	1			T4	7		T10	59		T19	13
valid_sources[0x3a]	420635	1			T7	12		T10	92		T19	6
valid_sources[0x3b]	424955	1			T4	2		T10	114		T19	16
valid_sources[0x3c]	424487	1			T10	84		T19	7		T24	6
valid_sources[0x3d]	646643	1			T10	97		T19	15		T24	4
valid_sources[0x3e]	484869	1			T9	1		T10	93		T19	6
valid_sources[0x3f]	422782	1			T7	1		T10	64		T19	6
valid_sources[0x40]	425419	1			T10	61		T19	14		T24	4
valid_sources[0x41]	427759	1			T4	1		T9	1		T10	107
valid_sources[0x42]	424348	1			T10	72		T19	12		T24	10
valid_sources[0x43]	422239	1			T10	85		T19	9		T24	8
valid_sources[0x44]	425762	1			T10	74		T19	5		T24	9
valid_sources[0x45]	2444679	1			T10	77		T19	5		T24	8
valid_sources[0x46]	420253	1			T9	1		T10	63		T19	7
valid_sources[0x47]	441903	1			T10	75		T19	3		T24	6
valid_sources[0x48]	425664	1			T10	67		T19	8		T24	9
valid_sources[0x49]	614159	1			T10	111		T19	5		T24	6
valid_sources[0x4a]	448727	1			T10	63		T19	6		T24	8
valid_sources[0x4b]	424084	1			T10	55		T19	1		T24	5
valid_sources[0x4c]	426719	1			T10	100		T19	6		T24	1
valid_sources[0x4d]	424133	1			T4	3		T10	62		T19	8
valid_sources[0x4e]	419265	1			T5	1		T9	1		T10	75
valid_sources[0x4f]	425160	1			T4	3		T10	64		T19	12
valid_sources[0x50]	422475	1			T7	7		T10	82		T19	9
valid_sources[0x51]	419259	1			T10	71		T19	7		T24	8
valid_sources[0x52]	422818	1			T7	11		T10	82		T19	10
valid_sources[0x53]	514484	1			T4	4		T7	2		T10	70
valid_sources[0x54]	427267	1			T9	2		T10	91		T19	5
valid_sources[0x55]	426657	1			T10	137		T19	3		T24	8
valid_sources[0x56]	442027	1			T4	1		T10	78		T19	7
valid_sources[0x57]	433921	1			T10	41		T19	9		T24	4
valid_sources[0x58]	423151	1			T10	94		T19	8		T24	7
valid_sources[0x59]	448352	1			T4	6		T7	1		T10	119
valid_sources[0x5a]	426695	1			T9	1		T10	63		T19	13
valid_sources[0x5b]	432567	1			T10	111		T19	6		T24	9
valid_sources[0x5c]	421348	1			T9	1		T10	101		T19	6
valid_sources[0x5d]	428561	1			T4	1		T7	5		T10	59
valid_sources[0x5e]	492864	1			T4	2		T9	1		T10	101
valid_sources[0x5f]	436335	1			T7	9		T10	87		T19	11
valid_sources[0x60]	425309	1			T10	82		T19	6		T24	5
valid_sources[0x61]	451461	1			T7	10		T10	95		T19	7
valid_sources[0x62]	424212	1			T10	113		T19	3		T24	2
valid_sources[0x63]	422332	1			T10	68		T19	10		T24	7
valid_sources[0x64]	2342173	1			T9	1		T10	68		T19	5
valid_sources[0x65]	421400	1			T7	16		T10	71		T19	11
valid_sources[0x66]	423651	1			T10	79		T19	6		T24	3
valid_sources[0x67]	1419887	1			T9	1		T10	55		T19	14
valid_sources[0x68]	863585	1			T4	5		T10	94		T19	4
valid_sources[0x69]	925575	1			T10	64		T19	9		T24	4
valid_sources[0x6a]	424167	1			T3	1317		T10	83		T19	9
valid_sources[0x6b]	438606	1			T9	1		T10	89		T19	10
valid_sources[0x6c]	427583	1			T10	84		T19	16		T24	6
valid_sources[0x6d]	417663	1			T10	88		T19	12		T24	3
valid_sources[0x6e]	427281	1			T9	1		T10	48		T19	7
valid_sources[0x6f]	424615	1			T10	95		T19	8		T24	4
valid_sources[0x70]	876354	1			T10	81		T19	9		T24	2
valid_sources[0x71]	424028	1			T10	81		T19	4		T24	6
valid_sources[0x72]	423784	1			T10	87		T19	5		T24	4
valid_sources[0x73]	417529	1			T7	1		T10	66		T19	13
valid_sources[0x74]	422136	1			T10	95		T19	7		T24	1
valid_sources[0x75]	1565990	1			T7	5		T10	65		T19	5
valid_sources[0x76]	442887	1			T4	4		T7	2		T9	1
valid_sources[0x77]	1409268	1			T7	11		T10	69		T19	4
valid_sources[0x78]	424603	1			T7	8		T10	64		T19	5
valid_sources[0x79]	420863	1			T10	61		T19	6		T24	4
valid_sources[0x7a]	423932	1			T10	67		T19	6		T24	5
valid_sources[0x7b]	810231	1			T10	106		T19	9		T24	7
valid_sources[0x7c]	1689883	1			T9	1		T10	57		T19	7
valid_sources[0x7d]	420224	1			T10	64		T19	9		T24	12
valid_sources[0x7e]	773258	1			T10	90		T19	10		T24	4
valid_sources[0x7f]	441430	1			T7	14		T10	88		T19	7
valid_sources[0x80]	426901	1			T10	130		T19	2		T24	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71891663

1

T1

1551

T2

1

T3

642

values[0x0]

all_enables

biggest_size

54216

1

T1

10

T3

13

T4

13

values[0x1]

all_enables

biggest_size

52425

1

T1

7

T3

4

T4

6