Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	138178	0	0
cfg0_rd_A	2147483647	1327	0	0
compare_lower0_0_rd_A	2147483647	1093	0	0
compare_upper0_0_rd_A	2147483647	1076	0	0
ctrl_rd_A	2147483647	920	0	0
intr_enable0_rd_A	2147483647	1712	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	138178	0	0
T11	116063	4784	0	0
T12	262893	11446	0	0
T13	169786	0	0	0
T15	0	6873	0	0
T25	0	6968	0	0
T26	0	6838	0	0
T27	0	15804	0	0
T28	0	148	0	0
T29	0	26187	0	0
T30	0	9570	0	0
T31	0	23533	0	0
T32	119236	0	0	0
T33	805089	0	0	0
T34	154943	0	0	0
T35	184996	0	0	0
T36	380683	0	0	0
T37	742926	0	0	0
T38	337113	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1327	0	0
T17	0	94	0	0
T18	0	196	0	0
T23	0	2	0	0
T28	5672	24	0	0
T29	633222	0	0	0
T39	0	68	0	0
T40	0	416	0	0
T41	0	80	0	0
T42	0	13	0	0
T43	0	60	0	0
T44	0	6	0	0
T45	965256	0	0	0
T46	101084	0	0	0
T47	292992	0	0	0
T48	205032	0	0	0
T49	376215	0	0	0
T50	101334	0	0	0
T51	106893	0	0	0
T52	289467	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1093	0	0
T17	0	46	0	0
T18	0	123	0	0
T23	0	4	0	0
T28	5672	21	0	0
T29	633222	0	0	0
T39	0	76	0	0
T40	0	455	0	0
T41	0	37	0	0
T42	0	6	0	0
T43	0	76	0	0
T45	965256	0	0	0
T46	101084	0	0	0
T47	292992	0	0	0
T48	205032	0	0	0
T49	376215	0	0	0
T50	101334	0	0	0
T51	106893	0	0	0
T52	289467	0	0	0
T53	0	8	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1076	0	0
T17	0	63	0	0
T18	0	142	0	0
T23	0	8	0	0
T28	5672	12	0	0
T29	633222	0	0	0
T39	0	69	0	0
T40	0	385	0	0
T41	0	51	0	0
T42	0	23	0	0
T43	0	62	0	0
T45	965256	0	0	0
T46	101084	0	0	0
T47	292992	0	0	0
T48	205032	0	0	0
T49	376215	0	0	0
T50	101334	0	0	0
T51	106893	0	0	0
T52	289467	0	0	0
T53	0	3	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	920	0	0
T17	0	73	0	0
T18	0	133	0	0
T23	0	7	0	0
T28	5672	17	0	0
T29	633222	0	0	0
T39	0	82	0	0
T40	0	292	0	0
T41	0	30	0	0
T42	0	14	0	0
T43	0	66	0	0
T45	965256	0	0	0
T46	101084	0	0	0
T47	292992	0	0	0
T48	205032	0	0	0
T49	376215	0	0	0
T50	101334	0	0	0
T51	106893	0	0	0
T52	289467	0	0	0
T53	0	1	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1712	0	0
T23	0	4	0	0
T28	5672	46	0	0
T29	633222	0	0	0
T39	0	165	0	0
T40	0	431	0	0
T45	965256	0	0	0
T46	101084	0	0	0
T47	292992	0	0	0
T48	205032	0	0	0
T49	376215	0	0	0
T50	101334	0	0	0
T51	106893	0	0	0
T52	289467	0	0	0
T54	0	4	0	0
T55	0	52	0	0
T56	0	22	0	0
T57	0	6	0	0
T58	0	116	0	0
T59	0	38	0	0