Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67324202	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

67471474

1

T1

1

T3

22

T5

6288

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	134659444	1			T1	1		T2	1		T3	30
values[0x0]	66052	1			T3	5		T5	8		T6	12
values[0x1]	70180	1			T3	4		T5	6		T6	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53801926	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

80993750

1

T1

1

T2

1

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	614494	1			T3	1		T8	90		T10	6
valid_sources[0x01]	390765	1			T3	1		T8	46		T11	36
valid_sources[0x02]	388695	1			T8	21		T10	5		T11	37
valid_sources[0x03]	391489	1			T6	1		T10	3		T11	49
valid_sources[0x04]	392720	1			T3	1		T8	29		T10	4
valid_sources[0x05]	2571152	1			T8	113		T10	11		T11	45
valid_sources[0x06]	394688	1			T6	2		T8	20		T11	53
valid_sources[0x07]	391659	1			T8	14		T10	5		T11	40
valid_sources[0x08]	407448	1			T8	32		T10	10		T11	31
valid_sources[0x09]	391933	1			T6	1		T8	2		T10	4
valid_sources[0x0a]	410599	1			T8	9		T10	3		T11	33
valid_sources[0x0b]	588244	1			T8	60		T10	4		T11	43
valid_sources[0x0c]	417086	1			T3	1		T8	20		T10	9
valid_sources[0x0d]	391875	1			T8	46		T10	6		T11	47
valid_sources[0x0e]	396857	1			T8	17		T10	6		T11	44
valid_sources[0x0f]	533084	1			T1	1		T8	27		T10	6
valid_sources[0x10]	394092	1			T8	77		T10	3		T11	35
valid_sources[0x11]	392314	1			T8	26		T10	3		T11	27
valid_sources[0x12]	888859	1			T3	1		T8	37		T11	37
valid_sources[0x13]	389633	1			T8	58		T10	5		T11	31
valid_sources[0x14]	390283	1			T6	3		T8	18		T10	6
valid_sources[0x15]	402165	1			T8	26		T10	5		T11	25
valid_sources[0x16]	393160	1			T3	1		T8	4		T10	7
valid_sources[0x17]	393245	1			T3	1		T8	32		T10	10
valid_sources[0x18]	394041	1			T8	50		T10	3		T11	49
valid_sources[0x19]	393207	1			T6	2		T8	19		T10	8
valid_sources[0x1a]	393234	1			T8	51		T10	6		T11	23
valid_sources[0x1b]	673206	1			T6	2		T8	45		T10	7
valid_sources[0x1c]	392553	1			T6	2		T8	11		T10	2
valid_sources[0x1d]	394064	1			T8	30		T10	3		T11	37
valid_sources[0x1e]	392731	1			T8	13		T10	4		T11	33
valid_sources[0x1f]	451493	1			T6	1		T8	1		T10	4
valid_sources[0x20]	393362	1			T8	41		T10	2		T11	36
valid_sources[0x21]	396245	1			T3	1		T10	2		T11	31
valid_sources[0x22]	404214	1			T8	28		T10	2		T11	21
valid_sources[0x23]	395198	1			T3	1		T8	19		T10	4
valid_sources[0x24]	389407	1			T8	44		T11	26		T12	164
valid_sources[0x25]	394536	1			T6	1		T10	4		T11	41
valid_sources[0x26]	393096	1			T3	1		T8	22		T10	3
valid_sources[0x27]	389744	1			T6	1		T8	55		T10	2
valid_sources[0x28]	577310	1			T8	49		T10	2		T11	47
valid_sources[0x29]	393296	1			T8	20		T11	27		T12	78
valid_sources[0x2a]	390938	1			T7	1		T8	102		T10	5
valid_sources[0x2b]	396506	1			T8	46		T10	2		T11	40
valid_sources[0x2c]	394118	1			T8	19		T10	1		T11	38
valid_sources[0x2d]	600792	1			T8	19		T11	29		T12	133
valid_sources[0x2e]	1338113	1			T3	1		T8	30		T10	4
valid_sources[0x2f]	393351	1			T8	15		T10	1		T11	32
valid_sources[0x30]	388470	1			T8	18		T10	10		T11	39
valid_sources[0x31]	392802	1			T8	4		T10	3		T11	53
valid_sources[0x32]	393588	1			T3	2		T8	61		T10	2
valid_sources[0x33]	391242	1			T8	28		T10	8		T11	29
valid_sources[0x34]	391568	1			T8	3		T10	3		T11	41
valid_sources[0x35]	393674	1			T8	20		T10	5		T11	45
valid_sources[0x36]	389609	1			T8	71		T10	5		T11	37
valid_sources[0x37]	390544	1			T8	16		T10	4		T11	20
valid_sources[0x38]	400879	1			T3	1		T8	55		T10	4
valid_sources[0x39]	2531143	1			T8	59		T10	1		T11	27
valid_sources[0x3a]	390664	1			T8	29		T10	5		T11	31
valid_sources[0x3b]	394922	1			T8	63		T10	5		T11	41
valid_sources[0x3c]	390637	1			T8	3		T10	5		T11	46
valid_sources[0x3d]	718507	1			T8	53		T10	8		T11	24
valid_sources[0x3e]	390412	1			T8	23		T10	10		T11	39
valid_sources[0x3f]	539409	1			T3	1		T8	13		T10	4
valid_sources[0x40]	393136	1			T8	23		T10	5		T11	22
valid_sources[0x41]	2451303	1			T8	37		T10	1		T11	29
valid_sources[0x42]	393814	1			T8	22		T10	1		T11	41
valid_sources[0x43]	391263	1			T8	16		T10	2		T11	31
valid_sources[0x44]	392321	1			T8	68		T10	5		T11	17
valid_sources[0x45]	393993	1			T8	32		T10	2		T11	30
valid_sources[0x46]	392313	1			T10	3		T11	38		T12	85
valid_sources[0x47]	405810	1			T8	40		T10	2		T11	38
valid_sources[0x48]	390580	1			T8	20		T10	1		T11	36
valid_sources[0x49]	411216	1			T8	2		T10	6		T11	49
valid_sources[0x4a]	937388	1			T10	6		T11	45		T12	3
valid_sources[0x4b]	391889	1			T3	1		T8	1		T10	2
valid_sources[0x4c]	391329	1			T8	156		T10	11		T11	36
valid_sources[0x4d]	391102	1			T8	10		T10	3		T11	38
valid_sources[0x4e]	388920	1			T8	24		T10	4		T11	42
valid_sources[0x4f]	1339310	1			T8	17		T10	4		T11	37
valid_sources[0x50]	389842	1			T10	3		T11	24		T12	69
valid_sources[0x51]	389996	1			T8	57		T10	3		T11	45
valid_sources[0x52]	591278	1			T8	41		T10	1		T11	42
valid_sources[0x53]	390494	1			T4	1		T8	39		T10	1
valid_sources[0x54]	390345	1			T8	47		T10	6		T11	37
valid_sources[0x55]	392799	1			T8	42		T10	9		T11	36
valid_sources[0x56]	392821	1			T8	40		T10	7		T11	39
valid_sources[0x57]	402571	1			T5	12664		T6	3		T8	16
valid_sources[0x58]	393389	1			T3	1		T8	18		T10	5
valid_sources[0x59]	394924	1			T3	1		T8	45		T10	4
valid_sources[0x5a]	391167	1			T3	1		T6	4		T8	54
valid_sources[0x5b]	390689	1			T8	25		T11	45		T12	303
valid_sources[0x5c]	418611	1			T8	19		T10	1		T11	27
valid_sources[0x5d]	871883	1			T8	89		T10	5		T11	45
valid_sources[0x5e]	391025	1			T6	1		T8	35		T10	2
valid_sources[0x5f]	402016	1			T8	41		T10	4		T11	41
valid_sources[0x60]	391051	1			T6	1		T10	4		T11	41
valid_sources[0x61]	391886	1			T8	27		T10	4		T11	38
valid_sources[0x62]	390929	1			T6	3		T8	33		T10	3
valid_sources[0x63]	391490	1			T8	36		T10	3		T11	38
valid_sources[0x64]	391279	1			T3	1		T8	31		T10	6
valid_sources[0x65]	392677	1			T8	56		T10	6		T11	38
valid_sources[0x66]	393451	1			T8	45		T10	8		T11	29
valid_sources[0x67]	394439	1			T8	25		T10	3		T11	32
valid_sources[0x68]	415710	1			T6	1		T8	36		T10	1
valid_sources[0x69]	393118	1			T8	31		T10	3		T11	38
valid_sources[0x6a]	390921	1			T8	64		T11	39		T12	99
valid_sources[0x6b]	391784	1			T8	16		T10	7		T11	31
valid_sources[0x6c]	393104	1			T8	26		T10	8		T11	44
valid_sources[0x6d]	390684	1			T8	7		T10	3		T11	34
valid_sources[0x6e]	1059273	1			T8	43		T10	5		T11	34
valid_sources[0x6f]	391427	1			T10	4		T11	32		T12	121
valid_sources[0x70]	2856096	1			T3	1		T8	7		T11	36
valid_sources[0x71]	391560	1			T8	34		T10	2		T11	39
valid_sources[0x72]	391494	1			T8	42		T10	3		T11	41
valid_sources[0x73]	390233	1			T6	1		T8	37		T10	9
valid_sources[0x74]	393257	1			T8	20		T10	1		T11	43
valid_sources[0x75]	399545	1			T8	3		T10	1		T11	36
valid_sources[0x76]	392310	1			T6	2		T8	2		T10	3
valid_sources[0x77]	394302	1			T3	1		T8	68		T10	1
valid_sources[0x78]	396396	1			T8	25		T10	7		T11	37
valid_sources[0x79]	413529	1			T8	31		T10	3		T11	39
valid_sources[0x7a]	390481	1			T8	30		T10	10		T11	35
valid_sources[0x7b]	392291	1			T8	35		T10	11		T11	23
valid_sources[0x7c]	389481	1			T8	60		T10	5		T11	37
valid_sources[0x7d]	389964	1			T8	9		T10	1		T11	35
valid_sources[0x7e]	392967	1			T8	8		T10	1		T11	34
valid_sources[0x7f]	387649	1			T8	22		T10	3		T11	55
valid_sources[0x80]	390595	1			T8	10		T10	3		T11	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67353385

1

T1

1

T3

17

T5

6277

values[0x0]

all_enables

biggest_size

60313

1

T3

3

T5

6

T6

2

values[0x1]

all_enables

biggest_size

57776

1

T3

2

T5

5

T6

6