Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	160859	0	0
cfg0_rd_A	2147483647	1770	0	0
compare_lower0_0_rd_A	2147483647	1804	0	0
compare_upper0_0_rd_A	2147483647	1738	0	0
ctrl_rd_A	2147483647	1804	0	0
intr_enable0_rd_A	2147483647	2696	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	160859	0	0
T11	310360	10082	0	0
T12	414160	0	0	0
T13	444222	15305	0	0
T14	0	3296	0	0
T18	871304	0	0	0
T22	418007	0	0	0
T23	0	17913	0	0
T24	0	20252	0	0
T25	0	3925	0	0
T26	0	18408	0	0
T27	0	5028	0	0
T28	0	14004	0	0
T29	0	7247	0	0
T30	204129	0	0	0
T31	324121	0	0	0
T32	151558	0	0	0
T33	502246	0	0	0
T34	886339	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1770	0	0
T14	121075	27	0	0
T20	0	4	0	0
T21	0	19	0	0
T25	0	33	0	0
T35	0	269	0	0
T36	0	52	0	0
T37	0	26	0	0
T38	0	5	0	0
T39	0	7	0	0
T40	0	6	0	0
T41	210803	0	0	0
T42	215443	0	0	0
T43	238109	0	0	0
T44	137362	0	0	0
T45	246133	0	0	0
T46	258365	0	0	0
T47	750009	0	0	0
T48	653739	0	0	0
T49	174914	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1804	0	0
T14	121075	50	0	0
T20	0	3	0	0
T21	0	10	0	0
T25	0	15	0	0
T35	0	298	0	0
T36	0	47	0	0
T37	0	35	0	0
T38	0	2	0	0
T39	0	3	0	0
T41	210803	0	0	0
T42	215443	0	0	0
T43	238109	0	0	0
T44	137362	0	0	0
T45	246133	0	0	0
T46	258365	0	0	0
T47	750009	0	0	0
T48	653739	0	0	0
T49	174914	0	0	0
T50	0	1	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1738	0	0
T14	121075	46	0	0
T20	0	8	0	0
T21	0	4	0	0
T25	0	29	0	0
T35	0	218	0	0
T36	0	47	0	0
T37	0	63	0	0
T38	0	8	0	0
T39	0	6	0	0
T41	210803	0	0	0
T42	215443	0	0	0
T43	238109	0	0	0
T44	137362	0	0	0
T45	246133	0	0	0
T46	258365	0	0	0
T47	750009	0	0	0
T48	653739	0	0	0
T49	174914	0	0	0
T50	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1804	0	0
T14	121075	63	0	0
T20	0	2	0	0
T21	0	12	0	0
T25	0	24	0	0
T35	0	191	0	0
T36	0	58	0	0
T37	0	71	0	0
T38	0	4	0	0
T39	0	7	0	0
T40	0	6	0	0
T41	210803	0	0	0
T42	215443	0	0	0
T43	238109	0	0	0
T44	137362	0	0	0
T45	246133	0	0	0
T46	258365	0	0	0
T47	750009	0	0	0
T48	653739	0	0	0
T49	174914	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2696	0	0
T14	121075	75	0	0
T25	0	72	0	0
T41	210803	0	0	0
T42	215443	0	0	0
T43	238109	0	0	0
T44	137362	0	0	0
T45	246133	0	0	0
T46	258365	0	0	0
T47	750009	0	0	0
T48	653739	0	0	0
T49	174914	0	0	0
T51	0	9	0	0
T52	0	48	0	0
T53	0	29	0	0
T54	0	4	0	0
T55	0	54	0	0
T56	0	32	0	0
T57	0	31	0	0
T58	0	41	0	0