Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	105481	0	0
cfg0_rd_A	2147483647	2262	0	0
compare_lower0_0_rd_A	2147483647	2047	0	0
compare_upper0_0_rd_A	2147483647	2020	0	0
ctrl_rd_A	2147483647	1924	0	0
intr_enable0_rd_A	2147483647	3272	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	105481	0	0
T11	361986	11421	0	0
T12	247579	7422	0	0
T13	146157	6768	0	0
T14	100028	0	0	0
T20	118241	5186	0	0
T21	282672	7838	0	0
T22	0	7972	0	0
T23	0	6062	0	0
T24	0	7042	0	0
T25	0	3432	0	0
T26	0	5762	0	0
T27	352412	0	0	0
T28	289139	0	0	0
T29	220423	0	0	0
T30	654107	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2262	0	0
T16	0	82	0	0
T21	282672	110	0	0
T23	0	68	0	0
T25	0	41	0	0
T26	0	101	0	0
T30	654107	0	0	0
T31	0	650	0	0
T32	0	17	0	0
T33	0	2	0	0
T34	0	71	0	0
T35	0	59	0	0
T36	185225	0	0	0
T37	231391	0	0	0
T38	551186	0	0	0
T39	457220	0	0	0
T40	463732	0	0	0
T41	456465	0	0	0
T42	943195	0	0	0
T43	568779	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2047	0	0
T16	0	79	0	0
T21	282672	143	0	0
T23	0	89	0	0
T25	0	55	0	0
T26	0	71	0	0
T30	654107	0	0	0
T31	0	660	0	0
T32	0	18	0	0
T34	0	61	0	0
T36	185225	0	0	0
T37	231391	0	0	0
T38	551186	0	0	0
T39	457220	0	0	0
T40	463732	0	0	0
T41	456465	0	0	0
T42	943195	0	0	0
T43	568779	0	0	0
T44	0	3	0	0
T45	0	1	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2020	0	0
T16	0	75	0	0
T21	282672	131	0	0
T23	0	58	0	0
T25	0	74	0	0
T26	0	104	0	0
T30	654107	0	0	0
T31	0	714	0	0
T32	0	16	0	0
T34	0	40	0	0
T35	0	83	0	0
T36	185225	0	0	0
T37	231391	0	0	0
T38	551186	0	0	0
T39	457220	0	0	0
T40	463732	0	0	0
T41	456465	0	0	0
T42	943195	0	0	0
T43	568779	0	0	0
T45	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1924	0	0
T16	0	49	0	0
T21	282672	121	0	0
T23	0	89	0	0
T25	0	56	0	0
T26	0	88	0	0
T30	654107	0	0	0
T31	0	588	0	0
T32	0	17	0	0
T33	0	5	0	0
T34	0	80	0	0
T36	185225	0	0	0
T37	231391	0	0	0
T38	551186	0	0	0
T39	457220	0	0	0
T40	463732	0	0	0
T41	456465	0	0	0
T42	943195	0	0	0
T43	568779	0	0	0
T44	0	3	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3272	0	0
T21	282672	233	0	0
T23	0	102	0	0
T25	0	89	0	0
T26	0	169	0	0
T30	654107	0	0	0
T36	185225	0	0	0
T37	231391	0	0	0
T38	551186	0	0	0
T39	457220	0	0	0
T40	463732	0	0	0
T41	456465	0	0	0
T42	943195	0	0	0
T43	568779	0	0	0
T46	0	73	0	0
T47	0	38	0	0
T48	0	42	0	0
T49	0	14	0	0
T50	0	65	0	0
T51	0	41	0	0