SPI_DEVICE Simulation Results

Monday May 15 2023 07:07:46 UTC

GitHub Revision: `3d5660d90`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 705130430

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.350s	81.731us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.440s	106.376us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.590s	92.154us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	42.980s	8.303ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	27.630s	6.476ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.200s	123.811us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.590s	92.154us	20	20	100.00
		spi_device_csr_aliasing	27.630s	6.476ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	13.680s	881.613us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	7.350s	75.931us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	44.334m	1.062s	49	50	98.00
V2	fifo_full	spi_device_fifo_full	35.883m	37.160ms	49	50	98.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	28.194m	1.348s	46	50	92.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	49.037m	204.700ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	49.037m	204.700ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.800s	31.664us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	0.960s	52.308us	49	50	98.00
V2	interrupts	spi_device_intr	2.003m	143.108ms	50	50	100.00
V2	abort	spi_device_abort	0.830s	18.115us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.600s	258.243us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	6.710s	4.557ms	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.440s	262.198us	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	1.246h	359.268ms	50	50	100.00
V2	perf	spi_device_perf	48.636m	206.003ms	49	50	98.00
V2	csb_read	spi_device_csb_read	0.870s	69.546us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	26.557us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	16.358us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	15.410s	855.456us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	15.410s	855.456us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	35.790s	75.215ms	50	50	100.00
		spi_device_tpm_sts_read	1.170s	205.114us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	2.933m	68.916ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	45.650s	31.680ms	50	50	100.00
		spi_device_flash_all	9.198m	505.244ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.460s	29.497ms	50	50	100.00
		spi_device_flash_all	9.198m	505.244ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.460s	29.497ms	50	50	100.00
		spi_device_flash_all	9.198m	505.244ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.198m	505.244ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	16.600s	9.005ms	50	50	100.00
		spi_device_flash_all	9.198m	505.244ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	16.600s	9.005ms	50	50	100.00
		spi_device_flash_all	9.198m	505.244ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	16.600s	9.005ms	50	50	100.00
		spi_device_flash_all	9.198m	505.244ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	16.600s	9.005ms	50	50	100.00
		spi_device_flash_all	9.198m	505.244ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	45.160s	14.759ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.039m	28.691ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.039m	28.691ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.039m	28.691ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.052m	14.694ms	49	50	98.00
		spi_device_read_buffer_direct	7.700s	6.908ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.039m	28.691ms	50	50	100.00
		spi_device_flash_all	9.198m	505.244ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.198m	505.244ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.198m	505.244ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	13.260s	13.092ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	13.260s	13.092ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.166m	333.432ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.176m	110.011ms	48	50	96.00
V2	stress_all	spi_device_stress_all	1.835h	603.869ms	12	50	24.00
V2	alert_test	spi_device_alert_test	0.800s	16.540us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	18.291us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.780s	74.532us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.780s	74.532us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.440s	106.376us	5	5	100.00
		spi_device_csr_rw	2.590s	92.154us	20	20	100.00
		spi_device_csr_aliasing	27.630s	6.476ms	5	5	100.00
		spi_device_same_csr_outstanding	4.580s	881.584us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.440s	106.376us	5	5	100.00
		spi_device_csr_rw	2.590s	92.154us	20	20	100.00
		spi_device_csr_aliasing	27.630s	6.476ms	5	5	100.00
		spi_device_same_csr_outstanding	4.580s	881.584us	20	20	100.00
V2		TOTAL			1631	1680	97.08
V2S	tl_intg_err	spi_device_sec_cm	1.210s	426.383us	5	5	100.00
		spi_device_tl_intg_err	24.190s	2.235ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.190s	2.235ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1771	1820	97.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	28	77.78
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.92	99.01	96.23	98.63	92.06	97.95	96.16	98.40

Failure Buckets

UVM_ERROR (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 33 failures:

Test spi_device_stress_all has 33 failures.

0.spi_device_stress_all.2063698563
Line 242, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 58474037187 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x99 [10011001] vs 0x34 [110100]) addr 0x42b87660 read out mismatch
  UVM_ERROR @ 58474037187 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xd8 [11011000] vs 0x2c [101100]) addr 0x42b87661 read out mismatch
  UVM_ERROR @ 58474037187 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xe7 [11100111] vs 0x21 [100001]) addr 0x42b87662 read out mismatch
  UVM_ERROR @ 58474037187 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x4 [100] vs 0xb1 [10110001]) addr 0x42b87663 read out mismatch
  UVM_ERROR @ 58476287187 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x6f [1101111] vs 0x7f [1111111]) addr 0x42b87664 read out mismatch

1.spi_device_stress_all.1467983644
Line 240, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 25738239231 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xe8 [11101000] vs 0x6e [1101110]) addr 0xf5fef844 read out mismatch
  UVM_ERROR @ 25738239231 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xc7 [11000111] vs 0x43 [1000011]) addr 0xf5fef845 read out mismatch
  UVM_ERROR @ 25738239231 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xd3 [11010011] vs 0xf6 [11110110]) addr 0xf5fef846 read out mismatch
  UVM_ERROR @ 25738239231 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xd3 [11010011] vs 0x55 [1010101]) addr 0xf5fef847 read out mismatch
  UVM_ERROR @ 25738885695 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x5b [1011011] vs 0x31 [110001]) addr 0xf5fef848 read out mismatch

... and 31 more failures.

Offending '(!dst_pulse_o)' has 4 failures:

Test spi_device_fifo_underflow_overflow has 4 failures.

13.spi_device_fifo_underflow_overflow.1563624530
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/13.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 1139420966 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  "../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 3812304583ps failed at 3812317404ps
      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 3812317404 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A

19.spi_device_fifo_underflow_overflow.2809669967
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 832254985 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  "../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 1854628845ps failed at 1854674300ps
      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 1854674300 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A

... and 2 more failures.

Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test spi_device_txrx has 1 failures.
  - 15.spi_device_txrx.2337460857
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/15.spi_device_txrx/latest/run.log
```
  Job ID: smart:2b1679e1-e9f0-4688-922f-8eb55468be48
```
- Test spi_device_fifo_full has 1 failures.
  - 17.spi_device_fifo_full.738431864
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/17.spi_device_fifo_full/latest/run.log
```
  Job ID: smart:0fc95247-29e7-46ca-adec-51af326c0063
```
- Test spi_device_perf has 1 failures.
  - 18.spi_device_perf.2800744174
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/18.spi_device_perf/latest/run.log
```
  Job ID: smart:90464159-ea13-4270-96ad-491b2533616e
```
- Test spi_device_stress_all has 1 failures.
  - 29.spi_device_stress_all.155094539
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_stress_all/latest/run.log
```
  Job ID: smart:b8a03e09-eb17-4b84-a9b2-b729a739082a
```

UVM_ERROR (spi_device_scoreboard.sv:971) [scoreboard] Check failed item.d_data == data_exp (* [*] vs * [*]) Compare SPI RX data, addr: * has 2 failures:

Test spi_device_stress_all has 2 failures.

2.spi_device_stress_all.2049199919
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 125359540095 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (1356959050 [0x50e18d4a] vs 1122263242 [0x42e460ca]) Compare SPI RX data, addr: 0xd0
  UVM_ERROR @ 125360206767 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3999286576 [0xee604530] vs 3561265507 [0xd4449963]) Compare SPI RX data, addr: 0xd4
  UVM_ERROR @ 125361095663 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (1122995405 [0x42ef8ccd] vs 3516635602 [0xd19b99d2]) Compare SPI RX data, addr: 0xd8
  UVM_ERROR @ 125365373475 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (2042298372 [0x79bb0004] vs 3448020825 [0xcd849f59]) Compare SPI RX data, addr: 0xdc
  UVM_ERROR @ 125366095703 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (462939053 [0x1b97e3ad] vs 543318746 [0x206262da]) Compare SPI RX data, addr: 0xe0

12.spi_device_stress_all.3465582728
Line 239, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/12.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 26594253367 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3166373797 [0xbcbb07a5] vs 3107742986 [0xb93c650a]) Compare SPI RX data, addr: 0x574
  UVM_ERROR @ 26594413367 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (4087989303 [0xf3a9c437] vs 2118241855 [0x7e41ce3f]) Compare SPI RX data, addr: 0x578
  UVM_ERROR @ 26595573367 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (2391150759 [0x8e8610a7] vs 4163331256 [0xf82764b8]) Compare SPI RX data, addr: 0x57c
  UVM_ERROR @ 26595813367 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (8 [0x8] vs 1396 [0x574]) get_sram_space_bytes::
  UVM_ERROR @ 26595973367 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3825151755 [0xe3ff2f0b] vs 903145699 [0x35d4e8e3]) Compare SPI RX data, addr: 0x580

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 2 failures.

5.spi_device_flash_and_tpm_min_idle.2276607385
Line 217, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_WARNING @ 1076439778 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 1076439778 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 1076439778 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 1076439778 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 1076439778 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

47.spi_device_flash_and_tpm_min_idle.2520614495
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_WARNING @ 97499752567 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 97499752567 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 97499752567 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 97499752567 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 97499752567 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

UVM_FATAL (spi_device_base_vseq.sv:395) [spi_device_intr_vseq] wait_for_tx_avail_bytes::SramSpaceAvail has 1 failures:
- Test spi_device_stress_all has 1 failures.
  - 3.spi_device_stress_all.2244057777
    Line 224, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 36648667149 ps: (spi_device_base_vseq.sv:395) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_tx_avail_bytes::SramSpaceAvail
  UVM_INFO @ 36648667149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (* [*] vs * [*]) get_sram_filled_bytes has 1 failures:

Test spi_device_stress_all has 1 failures.

9.spi_device_stress_all.2495544848
Line 247, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 624972485666 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (0 [0x0] vs 332 [0x14c]) get_sram_filled_bytes
  UVM_ERROR @ 624973263450 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (1801235344 [0x6b5cab90] vs 2468194966 [0x931daa96]) Compare SPI RX data, addr: 0x14c
  UVM_ERROR @ 624974430126 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3400175736 [0xcaaa9078] vs 465647477 [0x1bc13775]) Compare SPI RX data, addr: 0x150
  UVM_ERROR @ 624974763462 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (216821474 [0xcec6ee2] vs 2901595190 [0xacf2d436]) Compare SPI RX data, addr: 0x154
  UVM_ERROR @ 624977096814 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (0 [0x0] vs 344 [0x158]) get_sram_filled_bytes

UVM_FATAL (spi_device_scoreboard.sv:880) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 20.spi_device_flash_mode.719223496
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/20.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 10499259088 ps: (spi_device_scoreboard.sv:880) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 10499259088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (spi_device_scoreboard.sv:1372) [scoreboard] Check failed rx_word_q.size == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_rx_async_fifo_reset has 1 failures.
  - 37.spi_device_rx_async_fifo_reset.2970327263
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_rx_async_fifo_reset/latest/run.log
```
  UVM_ERROR @  99038687 ps: (spi_device_scoreboard.sv:1372) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
  UVM_INFO @  99038687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```