SPI_DEVICE Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_smoke 1.360s 180.761us 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.390s 241.243us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.730s 95.678us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 26.930s 2.288ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 26.460s 2.252ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.780s 288.645us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.730s 95.678us 20 20 100.00
spi_device_csr_aliasing 26.460s 2.252ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 15.880s 2.717ms 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 4.840s 179.864us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 base_random_seq spi_device_txrx 38.712m 175.041ms 50 50 100.00
V2 fifo_full spi_device_fifo_full 50.144m 114.400ms 50 50 100.00
V2 fifo_underflow_overflow spi_device_fifo_underflow_overflow 30.838m 114.045ms 49 50 98.00
V2 dummy_sck_and_dummy_csb spi_device_dummy_item_extra_dly 43.695m 91.363ms 50 50 100.00
V2 extra_delay_on_spi spi_device_dummy_item_extra_dly 43.695m 91.363ms 50 50 100.00
V2 tx_async_fifo_reset spi_device_tx_async_fifo_reset 0.810s 19.310us 50 50 100.00
V2 rx_async_fifo_reset spi_device_rx_async_fifo_reset 0.980s 182.683us 50 50 100.00
V2 interrupts spi_device_intr 1.690m 27.843ms 50 50 100.00
V2 abort spi_device_abort 0.810s 20.782us 50 50 100.00
V2 byte_transfer_on_spi spi_device_byte_transfer 4.130s 610.216us 50 50 100.00
V2 rx_timeout spi_device_rx_timeout 6.980s 900.051us 50 50 100.00
V2 bit_transfer_on_spi spi_device_bit_transfer 3.290s 377.777us 50 50 100.00
V2 extreme_fifo_setting spi_device_extreme_fifo_size 1.048h 316.078ms 50 50 100.00
V2 perf spi_device_perf 59.058m 52.920ms 50 50 100.00
V2 csb_read spi_device_csb_read 0.890s 162.104us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.130s 114.596us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.780s 16.852us 20 20 100.00
V2 tpm_read spi_device_tpm_rw 9.800s 1.071ms 50 50 100.00
V2 tpm_write spi_device_tpm_rw 9.800s 1.071ms 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 39.650s 13.991ms 50 50 100.00
spi_device_tpm_sts_read 1.160s 133.794us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 3.093m 10.728ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 47.430s 148.723ms 50 50 100.00
spi_device_flash_all 8.380m 115.962ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 1.204m 26.733ms 50 50 100.00
spi_device_flash_all 8.380m 115.962ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 1.204m 26.733ms 50 50 100.00
spi_device_flash_all 8.380m 115.962ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 8.380m 115.962ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 16.390s 4.722ms 50 50 100.00
spi_device_flash_all 8.380m 115.962ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 16.390s 4.722ms 50 50 100.00
spi_device_flash_all 8.380m 115.962ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 16.390s 4.722ms 50 50 100.00
spi_device_flash_all 8.380m 115.962ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 16.390s 4.722ms 50 50 100.00
spi_device_flash_all 8.380m 115.962ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 48.320s 89.141ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 1.162m 52.343ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 1.162m 52.343ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 1.162m 52.343ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.278m 68.225ms 49 50 98.00
spi_device_read_buffer_direct 8.420s 2.170ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 1.162m 52.343ms 50 50 100.00
spi_device_flash_all 8.380m 115.962ms 50 50 100.00
V2 quad_spi spi_device_flash_all 8.380m 115.962ms 50 50 100.00
V2 dual_spi spi_device_flash_all 8.380m 115.962ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 12.100s 3.408ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 12.100s 3.408ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 9.173m 620.367ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 10.510m 81.756ms 50 50 100.00
V2 stress_all spi_device_stress_all 1.032h 310.455ms 46 50 92.00
V2 alert_test spi_device_alert_test 0.770s 17.141us 50 50 100.00
V2 intr_test spi_device_intr_test 0.800s 41.543us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.940s 2.005ms 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.940s 2.005ms 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.390s 241.243us 5 5 100.00
spi_device_csr_rw 2.730s 95.678us 20 20 100.00
spi_device_csr_aliasing 26.460s 2.252ms 5 5 100.00
spi_device_same_csr_outstanding 4.590s 973.426us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.390s 241.243us 5 5 100.00
spi_device_csr_rw 2.730s 95.678us 20 20 100.00
spi_device_csr_aliasing 26.460s 2.252ms 5 5 100.00
spi_device_same_csr_outstanding 4.590s 973.426us 20 20 100.00
V2 TOTAL 1674 1680 99.64
V2S tl_intg_err spi_device_sec_cm 1.150s 1.480ms 5 5 100.00
spi_device_tl_intg_err 23.840s 2.267ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 23.840s 2.267ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1814 1820 99.67

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 36 36 33 91.67
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.97 99.07 96.32 98.63 92.06 98.05 96.16 98.49

Failure Buckets

Past Results