877a77116
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_device_smoke | 1.360s | 180.761us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.390s | 241.243us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_device_csr_rw | 2.730s | 95.678us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_device_csr_bit_bash | 26.930s | 2.288ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_device_csr_aliasing | 26.460s | 2.252ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 2.780s | 288.645us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.730s | 95.678us | 20 | 20 | 100.00 |
spi_device_csr_aliasing | 26.460s | 2.252ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_device_mem_walk | 15.880s | 2.717ms | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_device_mem_partial_access | 4.840s | 179.864us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | base_random_seq | spi_device_txrx | 38.712m | 175.041ms | 50 | 50 | 100.00 |
V2 | fifo_full | spi_device_fifo_full | 50.144m | 114.400ms | 50 | 50 | 100.00 |
V2 | fifo_underflow_overflow | spi_device_fifo_underflow_overflow | 30.838m | 114.045ms | 49 | 50 | 98.00 |
V2 | dummy_sck_and_dummy_csb | spi_device_dummy_item_extra_dly | 43.695m | 91.363ms | 50 | 50 | 100.00 |
V2 | extra_delay_on_spi | spi_device_dummy_item_extra_dly | 43.695m | 91.363ms | 50 | 50 | 100.00 |
V2 | tx_async_fifo_reset | spi_device_tx_async_fifo_reset | 0.810s | 19.310us | 50 | 50 | 100.00 |
V2 | rx_async_fifo_reset | spi_device_rx_async_fifo_reset | 0.980s | 182.683us | 50 | 50 | 100.00 |
V2 | interrupts | spi_device_intr | 1.690m | 27.843ms | 50 | 50 | 100.00 |
V2 | abort | spi_device_abort | 0.810s | 20.782us | 50 | 50 | 100.00 |
V2 | byte_transfer_on_spi | spi_device_byte_transfer | 4.130s | 610.216us | 50 | 50 | 100.00 |
V2 | rx_timeout | spi_device_rx_timeout | 6.980s | 900.051us | 50 | 50 | 100.00 |
V2 | bit_transfer_on_spi | spi_device_bit_transfer | 3.290s | 377.777us | 50 | 50 | 100.00 |
V2 | extreme_fifo_setting | spi_device_extreme_fifo_size | 1.048h | 316.078ms | 50 | 50 | 100.00 |
V2 | perf | spi_device_perf | 59.058m | 52.920ms | 50 | 50 | 100.00 |
V2 | csb_read | spi_device_csb_read | 0.890s | 162.104us | 50 | 50 | 100.00 |
V2 | mem_parity | spi_device_mem_parity | 1.130s | 114.596us | 20 | 20 | 100.00 |
V2 | mem_cfg | spi_device_ram_cfg | 0.780s | 16.852us | 20 | 20 | 100.00 |
V2 | tpm_read | spi_device_tpm_rw | 9.800s | 1.071ms | 50 | 50 | 100.00 |
V2 | tpm_write | spi_device_tpm_rw | 9.800s | 1.071ms | 50 | 50 | 100.00 |
V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 39.650s | 13.991ms | 50 | 50 | 100.00 |
spi_device_tpm_sts_read | 1.160s | 133.794us | 50 | 50 | 100.00 | ||
V2 | tpm_fully_random_case | spi_device_tpm_all | 3.093m | 10.728ms | 50 | 50 | 100.00 |
V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 47.430s | 148.723ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.380m | 115.962ms | 50 | 50 | 100.00 | ||
V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 1.204m | 26.733ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.380m | 115.962ms | 50 | 50 | 100.00 | ||
V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 1.204m | 26.733ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.380m | 115.962ms | 50 | 50 | 100.00 | ||
V2 | cmd_info_slots | spi_device_flash_all | 8.380m | 115.962ms | 50 | 50 | 100.00 |
V2 | cmd_read_status | spi_device_intercept | 16.390s | 4.722ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.380m | 115.962ms | 50 | 50 | 100.00 | ||
V2 | cmd_read_jedec | spi_device_intercept | 16.390s | 4.722ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.380m | 115.962ms | 50 | 50 | 100.00 | ||
V2 | cmd_read_sfdp | spi_device_intercept | 16.390s | 4.722ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.380m | 115.962ms | 50 | 50 | 100.00 | ||
V2 | cmd_fast_read | spi_device_intercept | 16.390s | 4.722ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.380m | 115.962ms | 50 | 50 | 100.00 | ||
V2 | flash_cmd_upload | spi_device_upload | 48.320s | 89.141ms | 50 | 50 | 100.00 |
V2 | mailbox_command | spi_device_mailbox | 1.162m | 52.343ms | 50 | 50 | 100.00 |
V2 | mailbox_cross_outside_command | spi_device_mailbox | 1.162m | 52.343ms | 50 | 50 | 100.00 |
V2 | mailbox_cross_inside_command | spi_device_mailbox | 1.162m | 52.343ms | 50 | 50 | 100.00 |
V2 | cmd_read_buffer | spi_device_flash_mode | 1.278m | 68.225ms | 49 | 50 | 98.00 |
spi_device_read_buffer_direct | 8.420s | 2.170ms | 50 | 50 | 100.00 | ||
V2 | cmd_dummy_cycle | spi_device_mailbox | 1.162m | 52.343ms | 50 | 50 | 100.00 |
spi_device_flash_all | 8.380m | 115.962ms | 50 | 50 | 100.00 | ||
V2 | quad_spi | spi_device_flash_all | 8.380m | 115.962ms | 50 | 50 | 100.00 |
V2 | dual_spi | spi_device_flash_all | 8.380m | 115.962ms | 50 | 50 | 100.00 |
V2 | 4b_3b_feature | spi_device_cfg_cmd | 12.100s | 3.408ms | 50 | 50 | 100.00 |
V2 | write_enable_disable | spi_device_cfg_cmd | 12.100s | 3.408ms | 50 | 50 | 100.00 |
V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 9.173m | 620.367ms | 50 | 50 | 100.00 |
V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 10.510m | 81.756ms | 50 | 50 | 100.00 |
V2 | stress_all | spi_device_stress_all | 1.032h | 310.455ms | 46 | 50 | 92.00 |
V2 | alert_test | spi_device_alert_test | 0.770s | 17.141us | 50 | 50 | 100.00 |
V2 | intr_test | spi_device_intr_test | 0.800s | 41.543us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_device_tl_errors | 5.940s | 2.005ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_device_tl_errors | 5.940s | 2.005ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.390s | 241.243us | 5 | 5 | 100.00 |
spi_device_csr_rw | 2.730s | 95.678us | 20 | 20 | 100.00 | ||
spi_device_csr_aliasing | 26.460s | 2.252ms | 5 | 5 | 100.00 | ||
spi_device_same_csr_outstanding | 4.590s | 973.426us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.390s | 241.243us | 5 | 5 | 100.00 |
spi_device_csr_rw | 2.730s | 95.678us | 20 | 20 | 100.00 | ||
spi_device_csr_aliasing | 26.460s | 2.252ms | 5 | 5 | 100.00 | ||
spi_device_same_csr_outstanding | 4.590s | 973.426us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1674 | 1680 | 99.64 | |||
V2S | tl_intg_err | spi_device_sec_cm | 1.150s | 1.480ms | 5 | 5 | 100.00 |
spi_device_tl_intg_err | 23.840s | 2.267ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 23.840s | 2.267ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 1814 | 1820 | 99.67 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 36 | 36 | 33 | 91.67 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 0 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
96.97 | 99.07 | 96.32 | 98.63 | 92.06 | 98.05 | 96.16 | 98.49 |
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.status.txf_full reset value: *
has 2 failures:
9.spi_device_stress_all.104249799
Line 246, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_stress_all/latest/run.log
UVM_ERROR @ 321906632363 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
UVM_ERROR @ 321907484969 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 100 [0x64]) get_sram_space_bytes::
UVM_ERROR @ 321909895897 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2370327106 [0x8d485242] vs 2311215775 [0x89c25a9f]) Compare SPI TX data
UVM_ERROR @ 321912020889 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2266403042 [0x871690e2] vs 1304178190 [0x4dbc2e0e]) Compare SPI TX data
UVM_INFO @ 321914442655 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
41.spi_device_stress_all.2743364160
Line 245, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/41.spi_device_stress_all/latest/run.log
UVM_ERROR @ 472126489609 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
UVM_ERROR @ 472131011321 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 424 [0x1a8]) get_sram_space_bytes::
UVM_ERROR @ 472133750435 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 428 [0x1ac]) get_sram_space_bytes::
UVM_ERROR @ 472144216894 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2013949308 [0x780a6d7c] vs 2163933685 [0x80fb01f5]) Compare SPI TX data
UVM_ERROR @ 472153955966 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2623697106 [0x9c6270d2] vs 665996084 [0x27b24b34]) Compare SPI TX data
Offending '(!dst_pulse_o)'
has 1 failures:
8.spi_device_fifo_underflow_overflow.182860365
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/8.spi_device_fifo_underflow_overflow/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 2554382907 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
"../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 3597907877ps failed at 3597928710ps
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3597928710 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_ERROR (mem_model.sv:35) [rx_mem] read from uninitialized addr *
has 1 failures:
19.spi_device_stress_all.2996098260
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_stress_all/latest/run.log
UVM_ERROR @ 344708794224 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x483
UVM_ERROR @ 344708794224 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x482
UVM_ERROR @ 344708794224 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x481
UVM_ERROR @ 344708794224 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x480
UVM_ERROR @ 344708794224 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (58405512 [0x37b3288] vs 3726616959 [0xde1fa97f]) Compare SPI RX data, addr: 0x480
UVM_ERROR (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (* [*] vs * [*]) get_sram_space_bytes::
has 1 failures:
30.spi_device_stress_all.3083564260
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/30.spi_device_stress_all/latest/run.log
UVM_ERROR @ 19356168093 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 1244 [0x4dc]) get_sram_space_bytes::
UVM_ERROR @ 19490102358 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (4184086171 [0xf964169b] vs 3940752585 [0xeae31cc9]) Compare SPI RX data, addr: 0x38c
UVM_ERROR @ 19490229123 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (950618670 [0x38a94a2e] vs 3458261714 [0xce20e2d2]) Compare SPI RX data, addr: 0x390
UVM_ERROR @ 19490369973 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (2727586247 [0xa293a9c7] vs 3739931180 [0xdeead22c]) Compare SPI RX data, addr: 0x394
UVM_ERROR @ 19490496738 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3485971150 [0xcfc7b2ce] vs 2290081629 [0x887fdf5d]) Compare SPI RX data, addr: 0x398
UVM_FATAL (spi_device_scoreboard.sv:890) [scoreboard] timeout occurred!
has 1 failures:
40.spi_device_flash_mode.1822079689
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_flash_mode/latest/run.log
UVM_FATAL @ 47723738751 ps: (spi_device_scoreboard.sv:890) [uvm_test_top.env.scoreboard] timeout occurred!
UVM_INFO @ 47723738751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---