SPI_DEVICE/2P Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.848m	418.033ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.520s	170.516us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.920s	461.925us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.330s	2.172ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.230s	2.539ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.350s	54.415us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.920s	461.925us	20	20	100.00
		spi_device_csr_aliasing	16.230s	2.539ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	11.422us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.580s	48.512us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.900s	19.055us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	57.358us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	17.934us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	9.560s	753.475us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.560s	753.475us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	29.690s	9.730ms	50	50	100.00
		spi_device_tpm_sts_read	1.250s	771.396us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	59.970s	24.526ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	36.970s	50.007ms	50	50	100.00
		spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	41.760s	15.108ms	50	50	100.00
		spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	41.760s	15.108ms	50	50	100.00
		spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	13.470s	16.282ms	50	50	100.00
		spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	13.470s	16.282ms	50	50	100.00
		spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	13.470s	16.282ms	50	50	100.00
		spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	13.470s	16.282ms	50	50	100.00
		spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	13.470s	16.282ms	50	50	100.00
		spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	38.920s	18.985ms	48	50	96.00
V2	mailbox_command	spi_device_mailbox	42.690s	163.147ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	42.690s	163.147ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	42.690s	163.147ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.107m	53.723ms	48	50	96.00
		spi_device_read_buffer_direct	7.120s	3.355ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	42.690s	163.147ms	50	50	100.00
		spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	8.439m	106.543ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	15.640s	21.033ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	15.640s	21.033ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.848m	418.033ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.778m	109.745ms	48	50	96.00
V2	stress_all	spi_device_stress_all	19.220m	324.208ms	49	50	98.00
V2	alert_test	spi_device_alert_test	0.800s	46.223us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	17.776us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.630s	56.614us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.630s	56.614us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.520s	170.516us	5	5	100.00
		spi_device_csr_rw	2.920s	461.925us	20	20	100.00
		spi_device_csr_aliasing	16.230s	2.539ms	5	5	100.00
		spi_device_same_csr_outstanding	5.270s	240.157us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.520s	170.516us	5	5	100.00
		spi_device_csr_rw	2.920s	461.925us	20	20	100.00
		spi_device_csr_aliasing	16.230s	2.539ms	5	5	100.00
		spi_device_same_csr_outstanding	5.270s	240.157us	20	20	100.00
V2		TOTAL			972	980	99.18
V2S	tl_intg_err	spi_device_sec_cm	1.180s	358.891us	5	5	100.00
		spi_device_tl_intg_err	28.340s	4.412ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	28.340s	4.412ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1112	1120	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	17	77.27
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.98	98.38	94.42	98.61	89.36	97.09	95.75	98.22

Failure Buckets

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 2 failures.

14.spi_device_flash_and_tpm_min_idle.3919229467817296056234162286541453255575864976931770664932466954315426856230
Line 285, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 5646582907 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 5829458550 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 18/19
  UVM_INFO @ 6118743689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.spi_device_flash_and_tpm_min_idle.66750254204906470035964449936060409579963689392855675578167352369861033398099
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 2436984715 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 2546015965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [spi_device_upload_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 2 failures:

Test spi_device_upload has 2 failures.

29.spi_device_upload.33925864615981717987582654046768778126615165032294325275451313206435958270225
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_upload/latest/run.log

  UVM_ERROR @ 327303242 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 338650220 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 9, test op = 0x4
  UVM_INFO @ 352778156 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 10, test op = 0x36
  UVM_INFO @ 412723242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.spi_device_upload.26882605794159455880211984317656371369767903999777260290994433854500021265132
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_upload/latest/run.log

  UVM_ERROR @ 3475939027 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 3725472167 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 1, test op = 0xd3
  UVM_INFO @ 3752106246 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0xd3
  UVM_INFO @ 4185607113 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0xf8
  UVM_INFO @ 5650443376 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0x5

UVM_ERROR (spi_device_scoreboard.sv:1024) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_stress_all has 1 failures.

3.spi_device_stress_all.59372204620345833924176545644378559589451160660182027655062098295104393050432
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 25962511358 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x526cb8) != exp '{'{other_status:'h22d778, wel:'h0, busy:'h0}}
  UVM_INFO @ 60093620084 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/7
  UVM_INFO @ 60526905365 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/16
  UVM_INFO @ 86745361430 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/7
  UVM_INFO @ 120180355694 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/7

UVM_FATAL (spi_device_scoreboard.sv:891) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 5.spi_device_flash_mode.85504939628079752322847622501781889485007181481372397355571180251785602330185
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 26288286511 ps: (spi_device_scoreboard.sv:891) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 26288286511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 13.spi_device_flash_mode.32387611632806911596300536656882772700522758016291666814571048393108708323744
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/13.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 335382990 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 2744428667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_all has 1 failures.

36.spi_device_flash_all.19546294892266379624657474457570635097935179725138164179550130567454470824230
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 662306739 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 835570373 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/5
  UVM_INFO @ 1231458235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---