| Name |
| /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3215520106 |
| /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1455996646 |
| /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4013021199 |
| /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2063597685 |
| /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3428335766 |
| /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1770933439 |
| /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.595830640 |
| /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.590073820 |
| /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3238693490 |
| /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1576076892 |
| /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.800094523 |
| /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4006544846 |
| /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.323820598 |
| /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1272936531 |
| /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2037886012 |
| /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2175230374 |
| /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.105766758 |
| /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1719352308 |
| /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1805301072 |
| /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1779654743 |
| /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3696491545 |
| /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3980985168 |
| /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.670458327 |
| /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2608551827 |
| /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4031346929 |
| /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3267380953 |
| /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.713768713 |
| /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1405477729 |
| /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2628859286 |
| /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2717953320 |
| /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.142679016 |
| /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.496256848 |
| /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1961706582 |
| /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.961078695 |
| /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1950207862 |
| /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2772204445 |
| /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.894015518 |
| /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2050792001 |
| /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2679465489 |
| /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3815666020 |
| /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4080933657 |
| /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2354515941 |
| /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.316886051 |
| /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3883470299 |
| /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3838651570 |
| /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1920954161 |
| /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1937345447 |
| /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.336611214 |
| /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2878784170 |
| /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1239072476 |
| /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.53133673 |
| /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3546158069 |
| /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.484268374 |
| /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1182632425 |
| /workspace/coverage/cover_reg_top/16.spi_device_intr_test.328384037 |
| /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1861510617 |
| /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.677770240 |
| /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.572193965 |
| /workspace/coverage/cover_reg_top/17.spi_device_intr_test.832341617 |
| /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2428471943 |
| /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2808401559 |
| /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3593164870 |
| /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.987688431 |
| /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.599361159 |
| /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1099406169 |
| /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4158544398 |
| /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2447745165 |
| /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.891140724 |
| /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2760198383 |
| /workspace/coverage/cover_reg_top/19.spi_device_intr_test.420107205 |
| /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.723398289 |
| /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2399897976 |
| /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3700487483 |
| /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2644152892 |
| /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3881134329 |
| /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.628314586 |
| /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2079156400 |
| /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.126508519 |
| /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4244466179 |
| /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.293785955 |
| /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.987792074 |
| /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4093216568 |
| /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.391300631 |
| /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1709512659 |
| /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3892947806 |
| /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2493179670 |
| /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3086665529 |
| /workspace/coverage/cover_reg_top/23.spi_device_intr_test.210908169 |
| /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4018914285 |
| /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2920640487 |
| /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2622144171 |
| /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2776098617 |
| /workspace/coverage/cover_reg_top/29.spi_device_intr_test.473958065 |
| /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3527569771 |
| /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2465104523 |
| /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3070196051 |
| /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3622867302 |
| /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3263211130 |
| /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1975228353 |
| /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2543529515 |
| /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3323244940 |
| /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.981434206 |
| /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.22627926 |
| /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1461815222 |
| /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1716710771 |
| /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2554553900 |
| /workspace/coverage/cover_reg_top/32.spi_device_intr_test.836842328 |
| /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2105273748 |
| /workspace/coverage/cover_reg_top/34.spi_device_intr_test.27387513 |
| /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3151397865 |
| /workspace/coverage/cover_reg_top/36.spi_device_intr_test.750118339 |
| /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2849878786 |
| /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2970181459 |
| /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1447814276 |
| /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.959608497 |
| /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3614224235 |
| /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3837771262 |
| /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2928515078 |
| /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1026011869 |
| /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3703377065 |
| /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3187853760 |
| /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1985532448 |
| /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2686254459 |
| /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2792861858 |
| /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2322370723 |
| /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3135597178 |
| /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3972009390 |
| /workspace/coverage/cover_reg_top/42.spi_device_intr_test.709809670 |
| /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2671220489 |
| /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1960766930 |
| /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2788388464 |
| /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2130581501 |
| /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2463360863 |
| /workspace/coverage/cover_reg_top/48.spi_device_intr_test.278612127 |
| /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1508268428 |
| /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.27349499 |
| /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2737540119 |
| /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3403596064 |
| /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3167808458 |
| /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2072079009 |
| /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4127465535 |
| /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3017725101 |
| /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1854449061 |
| /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1265641384 |
| /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2645342019 |
| /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2115333208 |
| /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4133608182 |
| /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3242451266 |
| /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3506990425 |
| /workspace/coverage/cover_reg_top/7.spi_device_intr_test.179733005 |
| /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.924301745 |
| /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1020791145 |
| /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1859319918 |
| /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3524060279 |
| /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1691881761 |
| /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2784862336 |
| /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2498722813 |
| /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2552113090 |
| /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2818888754 |
| /workspace/coverage/cover_reg_top/9.spi_device_intr_test.733728592 |
| /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.244162075 |
| /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.69687278 |
| /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1643696425 |
| /workspace/coverage/default/0.spi_device_alert_test.3531382468 |
| /workspace/coverage/default/0.spi_device_bit_transfer.2547166340 |
| /workspace/coverage/default/0.spi_device_byte_transfer.2306858886 |
| /workspace/coverage/default/0.spi_device_cfg_cmd.1764442727 |
| /workspace/coverage/default/0.spi_device_csb_read.3665416599 |
| /workspace/coverage/default/0.spi_device_dummy_item_extra_dly.3318708259 |
| /workspace/coverage/default/0.spi_device_extreme_fifo_size.1729876474 |
| /workspace/coverage/default/0.spi_device_fifo_full.3201278661 |
| /workspace/coverage/default/0.spi_device_fifo_underflow_overflow.2632768299 |
| /workspace/coverage/default/0.spi_device_flash_all.70155461 |
| /workspace/coverage/default/0.spi_device_flash_and_tpm.2819522364 |
| /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2292428826 |
| /workspace/coverage/default/0.spi_device_flash_mode.2962846282 |
| /workspace/coverage/default/0.spi_device_intercept.2265782737 |
| /workspace/coverage/default/0.spi_device_intr.1569738477 |
| /workspace/coverage/default/0.spi_device_mailbox.4121027065 |
| /workspace/coverage/default/0.spi_device_mem_parity.606138364 |
| /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2836833258 |
| /workspace/coverage/default/0.spi_device_perf.1688661193 |
| /workspace/coverage/default/0.spi_device_rx_timeout.3596982682 |
| /workspace/coverage/default/0.spi_device_smoke.1212123669 |
| /workspace/coverage/default/0.spi_device_tpm_all.3472905118 |
| /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2539671330 |
| /workspace/coverage/default/0.spi_device_tpm_rw.2794659763 |
| /workspace/coverage/default/0.spi_device_tpm_sts_read.2215930918 |
| /workspace/coverage/default/0.spi_device_tx_async_fifo_reset.4037649534 |
| /workspace/coverage/default/0.spi_device_txrx.3123229549 |
| /workspace/coverage/default/0.spi_device_upload.2725354600 |
| /workspace/coverage/default/1.spi_device_abort.1179029730 |
| /workspace/coverage/default/1.spi_device_alert_test.2350991528 |
| /workspace/coverage/default/1.spi_device_bit_transfer.239605789 |
| /workspace/coverage/default/1.spi_device_byte_transfer.3961826902 |
| /workspace/coverage/default/1.spi_device_cfg_cmd.1911861181 |
| /workspace/coverage/default/1.spi_device_csb_read.192888297 |
| /workspace/coverage/default/1.spi_device_dummy_item_extra_dly.294673806 |
| /workspace/coverage/default/1.spi_device_extreme_fifo_size.1601606840 |
| /workspace/coverage/default/1.spi_device_fifo_full.399514860 |
| /workspace/coverage/default/1.spi_device_fifo_underflow_overflow.1117331101 |
| /workspace/coverage/default/1.spi_device_flash_all.4235824682 |
| /workspace/coverage/default/1.spi_device_flash_and_tpm.1273663088 |
| /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3370180432 |
| /workspace/coverage/default/1.spi_device_flash_mode.354317893 |
| /workspace/coverage/default/1.spi_device_intercept.341160551 |
| /workspace/coverage/default/1.spi_device_intr.4137884530 |
| /workspace/coverage/default/1.spi_device_mailbox.1555177481 |
| /workspace/coverage/default/1.spi_device_mem_parity.1199332593 |
| /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4104272307 |
| /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1651655731 |
| /workspace/coverage/default/1.spi_device_perf.1299010919 |
| /workspace/coverage/default/1.spi_device_ram_cfg.3208846854 |
| /workspace/coverage/default/1.spi_device_read_buffer_direct.1965836968 |
| /workspace/coverage/default/1.spi_device_rx_async_fifo_reset.1066184690 |
| /workspace/coverage/default/1.spi_device_rx_timeout.2026701260 |
| /workspace/coverage/default/1.spi_device_sec_cm.2227003938 |
| /workspace/coverage/default/1.spi_device_smoke.1470061931 |
| /workspace/coverage/default/1.spi_device_stress_all.2678370485 |
| /workspace/coverage/default/1.spi_device_tpm_all.898608681 |
| /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1047843683 |
| /workspace/coverage/default/1.spi_device_tpm_rw.2396200932 |
| /workspace/coverage/default/1.spi_device_tpm_sts_read.703614732 |
| /workspace/coverage/default/1.spi_device_tx_async_fifo_reset.3654337430 |
| /workspace/coverage/default/1.spi_device_txrx.3072613261 |
| /workspace/coverage/default/1.spi_device_upload.2222998205 |
| /workspace/coverage/default/10.spi_device_abort.2987595212 |
| /workspace/coverage/default/10.spi_device_bit_transfer.2511563325 |
| /workspace/coverage/default/10.spi_device_byte_transfer.663492818 |
| /workspace/coverage/default/10.spi_device_cfg_cmd.2135353754 |
| /workspace/coverage/default/10.spi_device_csb_read.1626494577 |
| /workspace/coverage/default/10.spi_device_dummy_item_extra_dly.915167992 |
| /workspace/coverage/default/10.spi_device_extreme_fifo_size.2942074282 |
| /workspace/coverage/default/10.spi_device_fifo_full.196001994 |
| /workspace/coverage/default/10.spi_device_fifo_underflow_overflow.585444447 |
| /workspace/coverage/default/10.spi_device_flash_all.3622421977 |
| /workspace/coverage/default/10.spi_device_flash_and_tpm.1801254142 |
| /workspace/coverage/default/10.spi_device_flash_mode.4133846918 |
| /workspace/coverage/default/10.spi_device_intercept.4163887787 |
| /workspace/coverage/default/10.spi_device_intr.552569797 |
| /workspace/coverage/default/10.spi_device_mailbox.1855246783 |
| /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3211729630 |
| /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3959104661 |
| /workspace/coverage/default/10.spi_device_perf.1667444175 |
| /workspace/coverage/default/10.spi_device_ram_cfg.476284348 |
| /workspace/coverage/default/10.spi_device_read_buffer_direct.2821052471 |
| /workspace/coverage/default/10.spi_device_rx_async_fifo_reset.3457303304 |
| /workspace/coverage/default/10.spi_device_rx_timeout.4182320537 |
| /workspace/coverage/default/10.spi_device_smoke.752082602 |
| /workspace/coverage/default/10.spi_device_tpm_all.2047837807 |
| /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1399084555 |
| /workspace/coverage/default/10.spi_device_tpm_rw.3175714356 |
| /workspace/coverage/default/10.spi_device_tpm_sts_read.200903936 |
| /workspace/coverage/default/10.spi_device_tx_async_fifo_reset.2306596858 |
| /workspace/coverage/default/10.spi_device_txrx.569144442 |
| /workspace/coverage/default/10.spi_device_upload.3278421570 |
| /workspace/coverage/default/11.spi_device_abort.1242369975 |
| /workspace/coverage/default/11.spi_device_alert_test.1206269597 |
| /workspace/coverage/default/11.spi_device_bit_transfer.1048067622 |
| /workspace/coverage/default/11.spi_device_byte_transfer.73423929 |
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| /workspace/coverage/default/26.spi_device_smoke.3181381729 |
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| /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.35628893 |
| /workspace/coverage/default/26.spi_device_tpm_rw.2398312070 |
| /workspace/coverage/default/26.spi_device_tpm_sts_read.547354281 |
| /workspace/coverage/default/26.spi_device_tx_async_fifo_reset.1787204530 |
| /workspace/coverage/default/26.spi_device_txrx.197657256 |
| /workspace/coverage/default/26.spi_device_upload.2876340604 |
| /workspace/coverage/default/27.spi_device_abort.2582126976 |
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| /workspace/coverage/default/27.spi_device_bit_transfer.1940855041 |
| /workspace/coverage/default/27.spi_device_byte_transfer.364108749 |
| /workspace/coverage/default/27.spi_device_cfg_cmd.33768685 |
| /workspace/coverage/default/27.spi_device_csb_read.2664315112 |
| /workspace/coverage/default/27.spi_device_dummy_item_extra_dly.2702319578 |
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| /workspace/coverage/default/27.spi_device_flash_all.3127158835 |
| /workspace/coverage/default/27.spi_device_flash_and_tpm.2178094628 |
| /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2128955558 |
| /workspace/coverage/default/27.spi_device_intercept.1126070581 |
| /workspace/coverage/default/27.spi_device_intr.3108459659 |
| /workspace/coverage/default/27.spi_device_mailbox.2005601006 |
| /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.614771296 |
| /workspace/coverage/default/27.spi_device_pass_cmd_filtering.403615482 |
| /workspace/coverage/default/27.spi_device_perf.3414425560 |
| /workspace/coverage/default/27.spi_device_read_buffer_direct.878664855 |
| /workspace/coverage/default/27.spi_device_rx_async_fifo_reset.3295933037 |
| /workspace/coverage/default/27.spi_device_rx_timeout.4062342774 |
| /workspace/coverage/default/27.spi_device_smoke.3789368162 |
| /workspace/coverage/default/27.spi_device_stress_all.985709755 |
| /workspace/coverage/default/27.spi_device_tpm_all.3971226765 |
| /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.722291823 |
| /workspace/coverage/default/27.spi_device_tpm_rw.3832564815 |
| /workspace/coverage/default/27.spi_device_tpm_sts_read.3471372921 |
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| /workspace/coverage/default/36.spi_device_abort.2229134592 |
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| /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3520274250 |
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| /workspace/coverage/default/7.spi_device_txrx.602358185 |
| /workspace/coverage/default/7.spi_device_upload.2103596232 |
| /workspace/coverage/default/8.spi_device_abort.3530657230 |
| /workspace/coverage/default/8.spi_device_alert_test.246803523 |
| /workspace/coverage/default/8.spi_device_bit_transfer.2959981217 |
| /workspace/coverage/default/8.spi_device_byte_transfer.2302551286 |
| /workspace/coverage/default/8.spi_device_cfg_cmd.1406111885 |
| /workspace/coverage/default/8.spi_device_csb_read.3063696859 |
| /workspace/coverage/default/8.spi_device_dummy_item_extra_dly.2363573300 |
| /workspace/coverage/default/8.spi_device_extreme_fifo_size.4010112624 |
| /workspace/coverage/default/8.spi_device_fifo_full.4232684782 |
| /workspace/coverage/default/8.spi_device_fifo_underflow_overflow.3189992088 |
| /workspace/coverage/default/8.spi_device_flash_all.2695604340 |
| /workspace/coverage/default/8.spi_device_flash_and_tpm.3160558745 |
| /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3730264701 |
| /workspace/coverage/default/8.spi_device_flash_mode.757421149 |
| /workspace/coverage/default/8.spi_device_intercept.3203643406 |
| /workspace/coverage/default/8.spi_device_intr.3900558975 |
| /workspace/coverage/default/8.spi_device_mailbox.2782167985 |
| /workspace/coverage/default/8.spi_device_mem_parity.405734501 |
| /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4083287546 |
| /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1529579125 |
| /workspace/coverage/default/8.spi_device_perf.2359037302 |
| /workspace/coverage/default/8.spi_device_ram_cfg.166148326 |
| /workspace/coverage/default/8.spi_device_read_buffer_direct.2002441477 |
| /workspace/coverage/default/8.spi_device_rx_async_fifo_reset.4066853127 |
| /workspace/coverage/default/8.spi_device_rx_timeout.3067729689 |
| /workspace/coverage/default/8.spi_device_smoke.227928347 |
| /workspace/coverage/default/8.spi_device_stress_all.3912761158 |
| /workspace/coverage/default/8.spi_device_tpm_all.3068080420 |
| /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1736101817 |
| /workspace/coverage/default/8.spi_device_tpm_rw.267565456 |
| /workspace/coverage/default/8.spi_device_tpm_sts_read.4121985391 |
| /workspace/coverage/default/8.spi_device_tx_async_fifo_reset.2371188120 |
| /workspace/coverage/default/8.spi_device_txrx.3019789775 |
| /workspace/coverage/default/8.spi_device_upload.1913973200 |
| /workspace/coverage/default/9.spi_device_abort.1934567733 |
| /workspace/coverage/default/9.spi_device_alert_test.297106982 |
| /workspace/coverage/default/9.spi_device_bit_transfer.2961970337 |
| /workspace/coverage/default/9.spi_device_byte_transfer.3332438274 |
| /workspace/coverage/default/9.spi_device_cfg_cmd.908161939 |
| /workspace/coverage/default/9.spi_device_csb_read.2444335566 |
| /workspace/coverage/default/9.spi_device_dummy_item_extra_dly.1933043255 |
| /workspace/coverage/default/9.spi_device_extreme_fifo_size.894487407 |
| /workspace/coverage/default/9.spi_device_fifo_full.2553577370 |
| /workspace/coverage/default/9.spi_device_fifo_underflow_overflow.1367359324 |
| /workspace/coverage/default/9.spi_device_flash_all.2687711462 |
| /workspace/coverage/default/9.spi_device_flash_and_tpm.1720405240 |
| /workspace/coverage/default/9.spi_device_flash_mode.1289274397 |
| /workspace/coverage/default/9.spi_device_intercept.1284563460 |
| /workspace/coverage/default/9.spi_device_intr.749005164 |
| /workspace/coverage/default/9.spi_device_mailbox.1957007852 |
| /workspace/coverage/default/9.spi_device_mem_parity.2195135869 |
| /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.784715697 |
| /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1963635445 |
| /workspace/coverage/default/9.spi_device_perf.908595247 |
| /workspace/coverage/default/9.spi_device_ram_cfg.3265478488 |
| /workspace/coverage/default/9.spi_device_read_buffer_direct.3320299181 |
| /workspace/coverage/default/9.spi_device_rx_async_fifo_reset.1120527658 |
| /workspace/coverage/default/9.spi_device_rx_timeout.1433626396 |
| /workspace/coverage/default/9.spi_device_smoke.3838795412 |
| /workspace/coverage/default/9.spi_device_stress_all.1747551117 |
| /workspace/coverage/default/9.spi_device_tpm_all.1401238024 |
| /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.545335694 |
| /workspace/coverage/default/9.spi_device_tpm_rw.689154256 |
| /workspace/coverage/default/9.spi_device_tpm_sts_read.3232589480 |
| /workspace/coverage/default/9.spi_device_tx_async_fifo_reset.2832611280 |
| /workspace/coverage/default/9.spi_device_txrx.1936910070 |
| /workspace/coverage/default/9.spi_device_upload.2839978537 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T4 |
/workspace/coverage/default/44.spi_device_flash_mode.2854693054 |
|
|
May 26 01:59:10 AM PDT 23 |
May 26 01:59:28 AM PDT 23 |
1701887730 ps |
| T1 |
/workspace/coverage/default/10.spi_device_byte_transfer.663492818 |
|
|
May 26 01:51:51 AM PDT 23 |
May 26 01:51:55 AM PDT 23 |
372523339 ps |
| T2 |
/workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3071440764 |
|
|
May 26 01:53:43 AM PDT 23 |
May 26 01:54:13 AM PDT 23 |
17666943544 ps |
| T8 |
/workspace/coverage/default/48.spi_device_pass_cmd_filtering.3221520224 |
|
|
May 26 01:59:15 AM PDT 23 |
May 26 01:59:22 AM PDT 23 |
1689886934 ps |
| T10 |
/workspace/coverage/default/1.spi_device_upload.2222998205 |
|
|
May 26 01:50:02 AM PDT 23 |
May 26 01:50:08 AM PDT 23 |
1305805381 ps |
| T12 |
/workspace/coverage/default/9.spi_device_csb_read.2444335566 |
|
|
May 26 01:51:48 AM PDT 23 |
May 26 01:51:49 AM PDT 23 |
19532882 ps |
| T3 |
/workspace/coverage/default/42.spi_device_perf.2115117168 |
|
|
May 26 01:58:27 AM PDT 23 |
May 26 02:03:52 AM PDT 23 |
15154106597 ps |
| T7 |
/workspace/coverage/default/46.spi_device_fifo_full.1829889873 |
|
|
May 26 01:59:14 AM PDT 23 |
May 26 02:11:26 AM PDT 23 |
19997353975 ps |
| T13 |
/workspace/coverage/default/10.spi_device_alert_test.4280816053 |
|
|
May 26 01:51:57 AM PDT 23 |
May 26 01:51:58 AM PDT 23 |
156360113 ps |
| T14 |
/workspace/coverage/default/13.spi_device_extreme_fifo_size.2123984450 |
|
|
May 26 01:52:31 AM PDT 23 |
May 26 02:07:23 AM PDT 23 |
85262488187 ps |
| T9 |
/workspace/coverage/default/48.spi_device_fifo_underflow_overflow.920647235 |
|
|
May 26 01:59:16 AM PDT 23 |
May 26 02:09:46 AM PDT 23 |
365843062938 ps |
| T15 |
/workspace/coverage/default/15.spi_device_stress_all.824250514 |
|
|
May 26 01:52:38 AM PDT 23 |
May 26 02:27:48 AM PDT 23 |
236254855181 ps |
| T5 |
/workspace/coverage/default/31.spi_device_flash_all.2708455013 |
|
|
May 26 01:56:36 AM PDT 23 |
May 26 02:01:03 AM PDT 23 |
56564476868 ps |
| T11 |
/workspace/coverage/default/5.spi_device_intercept.414177524 |
|
|
May 26 01:50:54 AM PDT 23 |
May 26 01:51:00 AM PDT 23 |
456543561 ps |
| T16 |
/workspace/coverage/default/37.spi_device_upload.3551726271 |
|
|
May 26 01:57:41 AM PDT 23 |
May 26 01:57:52 AM PDT 23 |
4914143777 ps |
| T6 |
/workspace/coverage/default/48.spi_device_flash_and_tpm.4271680830 |
|
|
May 26 02:00:17 AM PDT 23 |
May 26 02:02:30 AM PDT 23 |
14729404059 ps |
| T30 |
/workspace/coverage/default/28.spi_device_rx_timeout.2074957978 |
|
|
May 26 01:56:01 AM PDT 23 |
May 26 01:56:08 AM PDT 23 |
767770416 ps |
| T31 |
/workspace/coverage/default/35.spi_device_fifo_underflow_overflow.2899775125 |
|
|
May 26 01:56:40 AM PDT 23 |
May 26 02:02:36 AM PDT 23 |
324971704169 ps |
| T18 |
/workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3273012082 |
|
|
May 26 01:56:28 AM PDT 23 |
May 26 01:56:33 AM PDT 23 |
385953310 ps |
| T32 |
/workspace/coverage/default/34.spi_device_rx_timeout.2973973406 |
|
|
May 26 01:56:43 AM PDT 23 |
May 26 01:56:49 AM PDT 23 |
3143124167 ps |
| T17 |
/workspace/coverage/default/0.spi_device_upload.2725354600 |
|
|
May 26 01:49:57 AM PDT 23 |
May 26 01:50:20 AM PDT 23 |
5713636893 ps |
| T41 |
/workspace/coverage/default/37.spi_device_intr.1169919171 |
|
|
May 26 01:57:36 AM PDT 23 |
May 26 01:59:20 AM PDT 23 |
56107409857 ps |
| T21 |
/workspace/coverage/default/21.spi_device_pass_cmd_filtering.1762321067 |
|
|
May 26 01:54:32 AM PDT 23 |
May 26 01:54:48 AM PDT 23 |
17850152019 ps |
| T147 |
/workspace/coverage/default/34.spi_device_txrx.3184069716 |
|
|
May 26 01:56:41 AM PDT 23 |
May 26 02:03:40 AM PDT 23 |
105452641931 ps |
| T77 |
/workspace/coverage/default/11.spi_device_intr.3971113362 |
|
|
May 26 01:51:59 AM PDT 23 |
May 26 01:53:34 AM PDT 23 |
25381860322 ps |
| T22 |
/workspace/coverage/default/11.spi_device_intercept.4222025830 |
|
|
May 26 01:51:55 AM PDT 23 |
May 26 01:51:59 AM PDT 23 |
524649259 ps |
| T34 |
/workspace/coverage/default/7.spi_device_read_buffer_direct.162655111 |
|
|
May 26 01:50:44 AM PDT 23 |
May 26 01:50:49 AM PDT 23 |
2657271532 ps |
| T110 |
/workspace/coverage/default/33.spi_device_mailbox.3746028704 |
|
|
May 26 01:56:40 AM PDT 23 |
May 26 01:57:22 AM PDT 23 |
24659979254 ps |
| T35 |
/workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1125582840 |
|
|
May 26 01:52:55 AM PDT 23 |
May 26 01:53:22 AM PDT 23 |
1523975645 ps |
| T207 |
/workspace/coverage/default/17.spi_device_cfg_cmd.1053310900 |
|
|
May 26 01:53:42 AM PDT 23 |
May 26 01:53:45 AM PDT 23 |
95349235 ps |
| T68 |
/workspace/coverage/default/16.spi_device_csb_read.3519393208 |
|
|
May 26 01:52:48 AM PDT 23 |
May 26 01:52:49 AM PDT 23 |
54196124 ps |
| T316 |
/workspace/coverage/default/24.spi_device_bit_transfer.1125669890 |
|
|
May 26 01:54:46 AM PDT 23 |
May 26 01:54:49 AM PDT 23 |
899653884 ps |
| T43 |
/workspace/coverage/default/6.spi_device_fifo_underflow_overflow.3455491949 |
|
|
May 26 01:50:54 AM PDT 23 |
May 26 02:01:47 AM PDT 23 |
135308235926 ps |
| T50 |
/workspace/coverage/default/47.spi_device_mailbox.1305175756 |
|
|
May 26 01:59:17 AM PDT 23 |
May 26 01:59:32 AM PDT 23 |
2734676633 ps |
| T36 |
/workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2163370080 |
|
|
May 26 01:53:51 AM PDT 23 |
May 26 01:55:41 AM PDT 23 |
7845383687 ps |
| T51 |
/workspace/coverage/default/7.spi_device_bit_transfer.3843829042 |
|
|
May 26 01:50:55 AM PDT 23 |
May 26 01:50:58 AM PDT 23 |
222441731 ps |
| T71 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4127465535 |
|
|
May 26 03:00:46 AM PDT 23 |
May 26 03:01:03 AM PDT 23 |
1259687690 ps |
| T72 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1709512659 |
|
|
May 26 03:00:34 AM PDT 23 |
May 26 03:00:42 AM PDT 23 |
582294829 ps |
| T73 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3700487483 |
|
|
May 26 03:01:35 AM PDT 23 |
May 26 03:01:51 AM PDT 23 |
1225349674 ps |
| T78 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.210908169 |
|
|
May 26 03:01:19 AM PDT 23 |
May 26 03:01:20 AM PDT 23 |
15914370 ps |
| T106 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1020791145 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:00:43 AM PDT 23 |
528296866 ps |
| T125 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3816409832 |
|
|
May 26 03:00:43 AM PDT 23 |
May 26 03:00:52 AM PDT 23 |
352574557 ps |
| T109 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2772204445 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:43 AM PDT 23 |
89046682 ps |
| T126 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3506990425 |
|
|
May 26 03:00:44 AM PDT 23 |
May 26 03:00:46 AM PDT 23 |
51928391 ps |
| T74 |
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.2266815488 |
|
|
May 26 03:00:48 AM PDT 23 |
May 26 03:00:48 AM PDT 23 |
45945913 ps |
| T123 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3449434810 |
|
|
May 26 03:01:11 AM PDT 23 |
May 26 03:01:32 AM PDT 23 |
3420085824 ps |
| T127 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2644152892 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:01:04 AM PDT 23 |
1387674433 ps |
| T130 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4132630699 |
|
|
May 26 03:00:33 AM PDT 23 |
May 26 03:00:49 AM PDT 23 |
4464950922 ps |
| T132 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1985532448 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:57 AM PDT 23 |
8142160046 ps |
| T133 |
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2686254459 |
|
|
May 26 03:00:46 AM PDT 23 |
May 26 03:00:50 AM PDT 23 |
253850440 ps |
| T134 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3238693490 |
|
|
May 26 03:00:39 AM PDT 23 |
May 26 03:00:44 AM PDT 23 |
245118388 ps |
| T135 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4006544846 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:00:49 AM PDT 23 |
828829302 ps |
| T136 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2465104523 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:01:12 AM PDT 23 |
590762697 ps |
| T137 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1750463602 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:45 AM PDT 23 |
277220751 ps |
| T107 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1576076892 |
|
|
May 26 03:00:35 AM PDT 23 |
May 26 03:00:38 AM PDT 23 |
128391981 ps |
| T108 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3649116553 |
|
|
May 26 03:00:41 AM PDT 23 |
May 26 03:00:44 AM PDT 23 |
46754551 ps |
| T75 |
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.1691881761 |
|
|
May 26 03:00:44 AM PDT 23 |
May 26 03:00:45 AM PDT 23 |
184784898 ps |
| T169 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.484268374 |
|
|
May 26 03:00:43 AM PDT 23 |
May 26 03:00:46 AM PDT 23 |
75914606 ps |
| T148 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.53133673 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:47 AM PDT 23 |
218871486 ps |
| T381 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2079156400 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:00:40 AM PDT 23 |
46341831 ps |
| T170 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3242451266 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:00:38 AM PDT 23 |
36864437 ps |
| T138 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3215520106 |
|
|
May 26 03:00:19 AM PDT 23 |
May 26 03:00:38 AM PDT 23 |
1905209509 ps |
| T382 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4093216568 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:00:41 AM PDT 23 |
137622691 ps |
| T111 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.391300631 |
|
|
May 26 03:00:35 AM PDT 23 |
May 26 03:00:37 AM PDT 23 |
212872673 ps |
| T76 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.420107205 |
|
|
May 26 03:01:17 AM PDT 23 |
May 26 03:01:21 AM PDT 23 |
20538685 ps |
| T383 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1859319918 |
|
|
May 26 03:00:38 AM PDT 23 |
May 26 03:00:40 AM PDT 23 |
52498529 ps |
| T384 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.924301745 |
|
|
May 26 03:00:41 AM PDT 23 |
May 26 03:00:45 AM PDT 23 |
267132411 ps |
| T128 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2322370723 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:00:43 AM PDT 23 |
449111601 ps |
| T380 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3622867302 |
|
|
May 26 03:00:33 AM PDT 23 |
May 26 03:00:35 AM PDT 23 |
32853674 ps |
| T129 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4031346929 |
|
|
May 26 03:00:48 AM PDT 23 |
May 26 03:01:08 AM PDT 23 |
1324711431 ps |
| T139 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.496256848 |
|
|
May 26 03:00:40 AM PDT 23 |
May 26 03:00:43 AM PDT 23 |
39376460 ps |
| T385 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1719352308 |
|
|
May 26 03:00:34 AM PDT 23 |
May 26 03:00:39 AM PDT 23 |
229553902 ps |
| T205 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.1961706582 |
|
|
May 26 03:00:48 AM PDT 23 |
May 26 03:00:49 AM PDT 23 |
31940643 ps |
| T140 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.628314586 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:00:38 AM PDT 23 |
17943173 ps |
| T174 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.4018914285 |
|
|
May 26 03:01:22 AM PDT 23 |
May 26 03:01:23 AM PDT 23 |
39998060 ps |
| T386 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.142679016 |
|
|
May 26 03:00:47 AM PDT 23 |
May 26 03:00:48 AM PDT 23 |
49114044 ps |
| T387 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3263211130 |
|
|
May 26 03:00:41 AM PDT 23 |
May 26 03:00:42 AM PDT 23 |
19091898 ps |
| T175 |
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.733728592 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:00:38 AM PDT 23 |
44900156 ps |
| T124 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1705473451 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:01:05 AM PDT 23 |
3368098780 ps |
| T113 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4212418951 |
|
|
May 26 03:00:48 AM PDT 23 |
May 26 03:00:52 AM PDT 23 |
632842249 ps |
| T131 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1779654743 |
|
|
May 26 03:00:21 AM PDT 23 |
May 26 03:00:24 AM PDT 23 |
283044357 ps |
| T141 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2760198383 |
|
|
May 26 03:00:41 AM PDT 23 |
May 26 03:00:43 AM PDT 23 |
78233504 ps |
| T171 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2928515078 |
|
|
May 26 03:00:46 AM PDT 23 |
May 26 03:00:49 AM PDT 23 |
41075589 ps |
| T172 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1937345447 |
|
|
May 26 03:00:47 AM PDT 23 |
May 26 03:01:08 AM PDT 23 |
12460531250 ps |
| T206 |
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.2849878786 |
|
|
May 26 03:01:18 AM PDT 23 |
May 26 03:01:20 AM PDT 23 |
40925747 ps |
| T388 |
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.2554553900 |
|
|
May 26 03:01:10 AM PDT 23 |
May 26 03:01:10 AM PDT 23 |
30998862 ps |
| T112 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2115333208 |
|
|
May 26 03:00:32 AM PDT 23 |
May 26 03:00:37 AM PDT 23 |
1060038949 ps |
| T389 |
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.2130581501 |
|
|
May 26 03:01:10 AM PDT 23 |
May 26 03:01:11 AM PDT 23 |
15163251 ps |
| T390 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2628859286 |
|
|
May 26 03:00:43 AM PDT 23 |
May 26 03:00:46 AM PDT 23 |
166930250 ps |
| T391 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2428471943 |
|
|
May 26 03:01:17 AM PDT 23 |
May 26 03:01:24 AM PDT 23 |
347311631 ps |
| T392 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4133608182 |
|
|
May 26 03:00:41 AM PDT 23 |
May 26 03:00:49 AM PDT 23 |
274695990 ps |
| T393 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.709809670 |
|
|
May 26 03:01:09 AM PDT 23 |
May 26 03:01:10 AM PDT 23 |
38813428 ps |
| T311 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.111888072 |
|
|
May 26 03:00:40 AM PDT 23 |
May 26 03:00:54 AM PDT 23 |
1211427999 ps |
| T142 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2543529515 |
|
|
May 26 03:00:46 AM PDT 23 |
May 26 03:00:52 AM PDT 23 |
470029294 ps |
| T394 |
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.2720316114 |
|
|
May 26 03:01:08 AM PDT 23 |
May 26 03:01:09 AM PDT 23 |
24159057 ps |
| T395 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.2970181459 |
|
|
May 26 03:01:14 AM PDT 23 |
May 26 03:01:15 AM PDT 23 |
18426331 ps |
| T173 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.891140724 |
|
|
May 26 03:01:09 AM PDT 23 |
May 26 03:01:11 AM PDT 23 |
77979853 ps |
| T396 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.959608497 |
|
|
May 26 03:00:46 AM PDT 23 |
May 26 03:00:56 AM PDT 23 |
1475601333 ps |
| T397 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.987792074 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:00:47 AM PDT 23 |
4660701005 ps |
| T143 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.894015518 |
|
|
May 26 03:01:12 AM PDT 23 |
May 26 03:01:14 AM PDT 23 |
90650286 ps |
| T144 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3524060279 |
|
|
May 26 03:00:34 AM PDT 23 |
May 26 03:00:36 AM PDT 23 |
50087170 ps |
| T398 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2784862336 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:00:41 AM PDT 23 |
63692734 ps |
| T145 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.323820598 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:00:39 AM PDT 23 |
83766159 ps |
| T399 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.179733005 |
|
|
May 26 03:00:44 AM PDT 23 |
May 26 03:00:45 AM PDT 23 |
23908605 ps |
| T400 |
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1099406169 |
|
|
May 26 03:01:17 AM PDT 23 |
May 26 03:01:23 AM PDT 23 |
93609290 ps |
| T315 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1643696425 |
|
|
May 26 03:00:49 AM PDT 23 |
May 26 03:00:57 AM PDT 23 |
859664029 ps |
| T401 |
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1861510617 |
|
|
May 26 03:01:24 AM PDT 23 |
May 26 03:01:28 AM PDT 23 |
111301145 ps |
| T402 |
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.836842328 |
|
|
May 26 03:01:11 AM PDT 23 |
May 26 03:01:12 AM PDT 23 |
13159728 ps |
| T403 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2552113090 |
|
|
May 26 03:00:44 AM PDT 23 |
May 26 03:00:45 AM PDT 23 |
22327445 ps |
| T404 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.2714119929 |
|
|
May 26 03:00:41 AM PDT 23 |
May 26 03:00:42 AM PDT 23 |
17966039 ps |
| T405 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2399897976 |
|
|
May 26 03:00:40 AM PDT 23 |
May 26 03:00:43 AM PDT 23 |
90534642 ps |
| T146 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2737540119 |
|
|
May 26 03:00:45 AM PDT 23 |
May 26 03:00:48 AM PDT 23 |
1480885245 ps |
| T406 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.27387513 |
|
|
May 26 03:01:19 AM PDT 23 |
May 26 03:01:20 AM PDT 23 |
12042031 ps |
| T407 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1920954161 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:47 AM PDT 23 |
158366958 ps |
| T408 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.126508519 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:00:38 AM PDT 23 |
27889615 ps |
| T409 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.2463360863 |
|
|
May 26 03:01:08 AM PDT 23 |
May 26 03:01:09 AM PDT 23 |
25750923 ps |
| T410 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.1716710771 |
|
|
May 26 03:01:11 AM PDT 23 |
May 26 03:01:12 AM PDT 23 |
63330523 ps |
| T411 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2608551827 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:44 AM PDT 23 |
32763549 ps |
| T412 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.278612127 |
|
|
May 26 03:01:14 AM PDT 23 |
May 26 03:01:15 AM PDT 23 |
17283025 ps |
| T413 |
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.2105273748 |
|
|
May 26 03:01:12 AM PDT 23 |
May 26 03:01:13 AM PDT 23 |
11682226 ps |
| T414 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.105766758 |
|
|
May 26 03:00:34 AM PDT 23 |
May 26 03:00:41 AM PDT 23 |
2164432565 ps |
| T415 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.572193965 |
|
|
May 26 03:01:17 AM PDT 23 |
May 26 03:01:21 AM PDT 23 |
18106296 ps |
| T416 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3696491545 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:00:58 AM PDT 23 |
3334924011 ps |
| T417 |
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3838651570 |
|
|
May 26 03:01:21 AM PDT 23 |
May 26 03:01:24 AM PDT 23 |
101775887 ps |
| T418 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.987688431 |
|
|
May 26 03:00:41 AM PDT 23 |
May 26 03:00:43 AM PDT 23 |
22551364 ps |
| T419 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.1960766930 |
|
|
May 26 03:01:19 AM PDT 23 |
May 26 03:01:20 AM PDT 23 |
37178160 ps |
| T420 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.3703377065 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:43 AM PDT 23 |
43901672 ps |
| T421 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4158544398 |
|
|
May 26 03:00:41 AM PDT 23 |
May 26 03:00:45 AM PDT 23 |
665616301 ps |
| T422 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2717953320 |
|
|
May 26 03:00:43 AM PDT 23 |
May 26 03:00:48 AM PDT 23 |
199096875 ps |
| T423 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4013021199 |
|
|
May 26 03:00:20 AM PDT 23 |
May 26 03:00:22 AM PDT 23 |
89380274 ps |
| T424 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.713768713 |
|
|
May 26 03:00:40 AM PDT 23 |
May 26 03:00:42 AM PDT 23 |
251124045 ps |
| T425 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.1265641384 |
|
|
May 26 03:00:43 AM PDT 23 |
May 26 03:00:44 AM PDT 23 |
15610404 ps |
| T426 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2679465489 |
|
|
May 26 03:00:48 AM PDT 23 |
May 26 03:00:51 AM PDT 23 |
290227773 ps |
| T427 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4080933657 |
|
|
May 26 03:00:48 AM PDT 23 |
May 26 03:01:06 AM PDT 23 |
6513055259 ps |
| T312 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3593164870 |
|
|
May 26 03:01:30 AM PDT 23 |
May 26 03:01:42 AM PDT 23 |
1267490421 ps |
| T428 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1182632425 |
|
|
May 26 03:01:10 AM PDT 23 |
May 26 03:01:13 AM PDT 23 |
1490738782 ps |
| T429 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.3135597178 |
|
|
May 26 03:01:10 AM PDT 23 |
May 26 03:01:11 AM PDT 23 |
28975214 ps |
| T430 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3017725101 |
|
|
May 26 03:00:38 AM PDT 23 |
May 26 03:00:40 AM PDT 23 |
50446785 ps |
| T431 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.832341617 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:43 AM PDT 23 |
29971808 ps |
| T432 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2818888754 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:44 AM PDT 23 |
154207549 ps |
| T433 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3815666020 |
|
|
May 26 03:00:43 AM PDT 23 |
May 26 03:00:45 AM PDT 23 |
106018792 ps |
| T434 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1854449061 |
|
|
May 26 03:00:34 AM PDT 23 |
May 26 03:00:36 AM PDT 23 |
225741933 ps |
| T435 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2808401559 |
|
|
May 26 03:00:41 AM PDT 23 |
May 26 03:00:43 AM PDT 23 |
212904866 ps |
| T436 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2792861858 |
|
|
May 26 03:00:41 AM PDT 23 |
May 26 03:00:43 AM PDT 23 |
66221263 ps |
| T437 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3614224235 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:01:09 AM PDT 23 |
7795591870 ps |
| T438 |
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.3883470299 |
|
|
May 26 03:01:17 AM PDT 23 |
May 26 03:01:21 AM PDT 23 |
38730735 ps |
| T439 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.3086665529 |
|
|
May 26 03:01:18 AM PDT 23 |
May 26 03:01:20 AM PDT 23 |
38160972 ps |
| T440 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3267380953 |
|
|
May 26 03:00:48 AM PDT 23 |
May 26 03:00:50 AM PDT 23 |
201621774 ps |
| T441 |
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.2671220489 |
|
|
May 26 03:01:20 AM PDT 23 |
May 26 03:01:21 AM PDT 23 |
48025693 ps |
| T442 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3167808458 |
|
|
May 26 03:00:46 AM PDT 23 |
May 26 03:00:50 AM PDT 23 |
697287110 ps |
| T443 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.961078695 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:45 AM PDT 23 |
90784125 ps |
| T444 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1026011869 |
|
|
May 26 03:00:46 AM PDT 23 |
May 26 03:00:48 AM PDT 23 |
516308822 ps |
| T445 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1448147881 |
|
|
May 26 03:00:40 AM PDT 23 |
May 26 03:00:42 AM PDT 23 |
182373836 ps |
| T446 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2354515941 |
|
|
May 26 03:01:12 AM PDT 23 |
May 26 03:01:14 AM PDT 23 |
72743371 ps |
| T447 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.293785955 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:00:39 AM PDT 23 |
123044226 ps |
| T448 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3837771262 |
|
|
May 26 03:00:40 AM PDT 23 |
May 26 03:00:42 AM PDT 23 |
83656335 ps |
| T449 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.336611214 |
|
|
May 26 03:01:24 AM PDT 23 |
May 26 03:01:28 AM PDT 23 |
29821998 ps |
| T450 |
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.473958065 |
|
|
May 26 03:01:09 AM PDT 23 |
May 26 03:01:10 AM PDT 23 |
44804327 ps |
| T451 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3428335766 |
|
|
May 26 03:00:21 AM PDT 23 |
May 26 03:00:24 AM PDT 23 |
221262173 ps |
| T452 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.800094523 |
|
|
May 26 03:00:32 AM PDT 23 |
May 26 03:00:52 AM PDT 23 |
1019256091 ps |
| T453 |
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1805301072 |
|
|
May 26 03:00:34 AM PDT 23 |
May 26 03:00:37 AM PDT 23 |
588160879 ps |
| T454 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3187853760 |
|
|
May 26 03:00:34 AM PDT 23 |
May 26 03:00:37 AM PDT 23 |
75791163 ps |
| T455 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1405477729 |
|
|
May 26 03:00:48 AM PDT 23 |
May 26 03:00:50 AM PDT 23 |
28127586 ps |
| T456 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.590073820 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:00:45 AM PDT 23 |
2144591834 ps |
| T457 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.244162075 |
|
|
May 26 03:00:47 AM PDT 23 |
May 26 03:00:50 AM PDT 23 |
352358502 ps |
| T458 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.2622144171 |
|
|
May 26 03:01:12 AM PDT 23 |
May 26 03:01:13 AM PDT 23 |
13336032 ps |
| T459 |
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.3403596064 |
|
|
May 26 03:00:46 AM PDT 23 |
May 26 03:00:47 AM PDT 23 |
13641693 ps |
| T460 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.27349499 |
|
|
May 26 03:00:33 AM PDT 23 |
May 26 03:00:35 AM PDT 23 |
116391466 ps |
| T461 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2063597685 |
|
|
May 26 03:00:33 AM PDT 23 |
May 26 03:00:36 AM PDT 23 |
32143099 ps |
| T462 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3070196051 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:44 AM PDT 23 |
79698887 ps |
| T463 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3323244940 |
|
|
May 26 03:00:40 AM PDT 23 |
May 26 03:00:54 AM PDT 23 |
2726476433 ps |
| T464 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.4244466179 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:00:38 AM PDT 23 |
25273181 ps |
| T465 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.1447814276 |
|
|
May 26 03:01:08 AM PDT 23 |
May 26 03:01:09 AM PDT 23 |
11713978 ps |
| T466 |
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.1508268428 |
|
|
May 26 03:01:08 AM PDT 23 |
May 26 03:01:09 AM PDT 23 |
16256140 ps |
| T467 |
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.3151397865 |
|
|
May 26 03:01:19 AM PDT 23 |
May 26 03:01:20 AM PDT 23 |
40642645 ps |
| T468 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.69687278 |
|
|
May 26 03:00:41 AM PDT 23 |
May 26 03:00:46 AM PDT 23 |
336962118 ps |
| T469 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3881134329 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:01:00 AM PDT 23 |
683773143 ps |
| T470 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.981434206 |
|
|
May 26 03:00:40 AM PDT 23 |
May 26 03:00:44 AM PDT 23 |
237936284 ps |
| T471 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1455996646 |
|
|
May 26 03:00:22 AM PDT 23 |
May 26 03:00:47 AM PDT 23 |
24617713734 ps |
| T472 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3972009390 |
|
|
May 26 03:01:11 AM PDT 23 |
May 26 03:01:12 AM PDT 23 |
14405070 ps |
| T473 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.316886051 |
|
|
May 26 03:00:43 AM PDT 23 |
May 26 03:00:45 AM PDT 23 |
69769282 ps |
| T474 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1272936531 |
|
|
May 26 03:00:35 AM PDT 23 |
May 26 03:00:38 AM PDT 23 |
65577636 ps |
| T475 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.599361159 |
|
|
May 26 03:01:17 AM PDT 23 |
May 26 03:01:23 AM PDT 23 |
972291244 ps |
| T476 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1461815222 |
|
|
May 26 03:00:40 AM PDT 23 |
May 26 03:00:52 AM PDT 23 |
416827763 ps |
| T477 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.670458327 |
|
|
May 26 03:00:48 AM PDT 23 |
May 26 03:00:52 AM PDT 23 |
227557242 ps |
| T478 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2037886012 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:00:38 AM PDT 23 |
269552907 ps |
| T479 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.1770933439 |
|
|
May 26 03:00:22 AM PDT 23 |
May 26 03:00:23 AM PDT 23 |
24220183 ps |
| T313 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1950207862 |
|
|
May 26 03:00:43 AM PDT 23 |
May 26 03:00:52 AM PDT 23 |
1007217150 ps |
| T314 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2447745165 |
|
|
May 26 03:01:17 AM PDT 23 |
May 26 03:01:39 AM PDT 23 |
825785737 ps |
| T480 |
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.2175230374 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:00:37 AM PDT 23 |
16678559 ps |
| T481 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.22627926 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:00:39 AM PDT 23 |
49757094 ps |
| T482 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2498722813 |
|
|
May 26 03:00:39 AM PDT 23 |
May 26 03:00:48 AM PDT 23 |
3109631259 ps |
| T483 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3980985168 |
|
|
May 26 03:00:39 AM PDT 23 |
May 26 03:00:42 AM PDT 23 |
94520527 ps |
| T484 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.750118339 |
|
|
May 26 03:01:18 AM PDT 23 |
May 26 03:01:20 AM PDT 23 |
17168470 ps |
| T485 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2645342019 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:46 AM PDT 23 |
1831049714 ps |
| T486 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.2050792001 |
|
|
May 26 03:00:48 AM PDT 23 |
May 26 03:00:48 AM PDT 23 |
25895423 ps |
| T487 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.2788388464 |
|
|
May 26 03:01:18 AM PDT 23 |
May 26 03:01:20 AM PDT 23 |
25002133 ps |
| T488 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3546158069 |
|
|
May 26 03:01:10 AM PDT 23 |
May 26 03:01:15 AM PDT 23 |
144830928 ps |
| T489 |
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.2920640487 |
|
|
May 26 03:01:20 AM PDT 23 |
May 26 03:01:22 AM PDT 23 |
24618930 ps |
| T490 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.3892947806 |
|
|
May 26 03:01:19 AM PDT 23 |
May 26 03:01:20 AM PDT 23 |
15132888 ps |
| T491 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.1975228353 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:00:38 AM PDT 23 |
13657145 ps |
| T492 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.328384037 |
|
|
May 26 03:01:11 AM PDT 23 |
May 26 03:01:12 AM PDT 23 |
143042052 ps |
| T493 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.2493179670 |
|
|
May 26 03:01:22 AM PDT 23 |
May 26 03:01:23 AM PDT 23 |
53113784 ps |
| T494 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.595830640 |
|
|
May 26 03:00:37 AM PDT 23 |
May 26 03:00:40 AM PDT 23 |
61320373 ps |
| T495 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.677770240 |
|
|
May 26 03:01:10 AM PDT 23 |
May 26 03:01:14 AM PDT 23 |
576684755 ps |
| T496 |
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.723398289 |
|
|
May 26 03:01:08 AM PDT 23 |
May 26 03:01:13 AM PDT 23 |
627359224 ps |
| T497 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3527569771 |
|
|
May 26 03:00:40 AM PDT 23 |
May 26 03:00:57 AM PDT 23 |
800521357 ps |
| T498 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.2776098617 |
|
|
May 26 03:01:19 AM PDT 23 |
May 26 03:01:20 AM PDT 23 |
12261383 ps |
| T499 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2072079009 |
|
|
May 26 03:00:42 AM PDT 23 |
May 26 03:00:46 AM PDT 23 |
47769468 ps |
| T500 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2878784170 |
|
|
May 26 03:00:36 AM PDT 23 |
May 26 03:00:38 AM PDT 23 |
97102799 ps |
| T501 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.1239072476 |
|
|
May 26 03:00:43 AM PDT 23 |
May 26 03:00:44 AM PDT 23 |
13898011 ps |
| T204 |
/workspace/coverage/default/16.spi_device_mailbox.14479964 |
|
|
May 26 01:52:43 AM PDT 23 |
May 26 01:52:54 AM PDT 23 |
1105305524 ps |
| T319 |
/workspace/coverage/default/13.spi_device_fifo_full.1288315457 |
|
|
May 26 01:52:33 AM PDT 23 |
May 26 01:59:36 AM PDT 23 |
27585251200 ps |
| T19 |
/workspace/coverage/default/43.spi_device_flash_and_tpm.3771804933 |
|
|
May 26 01:58:37 AM PDT 23 |
May 26 02:05:59 AM PDT 23 |
126447688224 ps |
| T33 |
/workspace/coverage/default/25.spi_device_rx_timeout.2149200280 |
|
|
May 26 01:54:56 AM PDT 23 |
May 26 01:55:01 AM PDT 23 |
619776855 ps |
| T114 |
/workspace/coverage/default/26.spi_device_stress_all.1273568979 |
|
|
May 26 01:55:42 AM PDT 23 |
May 26 02:11:19 AM PDT 23 |
172488817979 ps |
| T42 |
/workspace/coverage/default/8.spi_device_flash_and_tpm.3160558745 |
|
|
May 26 01:51:45 AM PDT 23 |
May 26 01:58:06 AM PDT 23 |
116105025634 ps |
| T320 |
/workspace/coverage/default/3.spi_device_bit_transfer.1684248360 |
|
|
May 26 01:50:20 AM PDT 23 |
May 26 01:50:25 AM PDT 23 |
1096426867 ps |
| T96 |
/workspace/coverage/default/41.spi_device_tpm_all.2848124068 |
|
|
May 26 01:58:13 AM PDT 23 |
May 26 01:58:33 AM PDT 23 |
3437242430 ps |
| T97 |
/workspace/coverage/default/6.spi_device_tpm_rw.936213937 |
|
|
May 26 01:50:52 AM PDT 23 |
May 26 01:50:53 AM PDT 23 |
107816532 ps |
| T321 |
/workspace/coverage/default/32.spi_device_rx_timeout.1204521421 |
|
|
May 26 01:56:33 AM PDT 23 |
May 26 01:56:38 AM PDT 23 |
2299514426 ps |
| T98 |
/workspace/coverage/default/25.spi_device_tpm_read_hw_reg.738640753 |
|
|
May 26 01:54:45 AM PDT 23 |
May 26 01:54:51 AM PDT 23 |
3226650611 ps |
| T38 |
/workspace/coverage/default/14.spi_device_mem_parity.1860347551 |
|
|
May 26 01:52:30 AM PDT 23 |
May 26 01:52:31 AM PDT 23 |
94649863 ps |
| T502 |
/workspace/coverage/default/33.spi_device_dummy_item_extra_dly.938777816 |
|
|
May 26 01:56:27 AM PDT 23 |
May 26 02:01:52 AM PDT 23 |
19716266226 ps |
| T99 |
/workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1233026982 |
|
|
May 26 01:52:37 AM PDT 23 |
May 26 01:52:58 AM PDT 23 |
28056890884 ps |
| T503 |
/workspace/coverage/default/21.spi_device_intercept.628440395 |
|
|
May 26 01:54:42 AM PDT 23 |
May 26 01:54:55 AM PDT 23 |
18093048636 ps |
| T504 |
/workspace/coverage/default/13.spi_device_rx_timeout.1012561184 |
|
|
May 26 01:52:35 AM PDT 23 |
May 26 01:52:41 AM PDT 23 |
1272403361 ps |
| T317 |
/workspace/coverage/default/45.spi_device_extreme_fifo_size.3126279512 |
|
|
May 26 01:59:09 AM PDT 23 |
May 26 02:01:46 AM PDT 23 |
21591664158 ps |
| T208 |
/workspace/coverage/default/42.spi_device_mailbox.3585868192 |
|
|
May 26 01:58:27 AM PDT 23 |
May 26 01:58:46 AM PDT 23 |
29018498056 ps |
| T203 |
/workspace/coverage/default/18.spi_device_intercept.3919942559 |
|
|
May 26 01:53:41 AM PDT 23 |
May 26 01:53:46 AM PDT 23 |
796099278 ps |
| T44 |
/workspace/coverage/default/2.spi_device_txrx.3307945770 |
|
|
May 26 01:50:06 AM PDT 23 |
May 26 01:57:21 AM PDT 23 |
25164141217 ps |
| T318 |
/workspace/coverage/default/23.spi_device_smoke.592810606 |
|
|
May 26 01:54:44 AM PDT 23 |
May 26 01:54:45 AM PDT 23 |
31443993 ps |
| T185 |
/workspace/coverage/default/23.spi_device_extreme_fifo_size.3713574987 |
|
|
May 26 01:54:42 AM PDT 23 |
May 26 02:18:11 AM PDT 23 |
176764537080 ps |
| T65 |
/workspace/coverage/default/0.spi_device_rx_async_fifo_reset.1012412583 |
|
|
May 26 01:50:00 AM PDT 23 |
May 26 01:50:01 AM PDT 23 |
142053939 ps |
| T102 |
/workspace/coverage/default/11.spi_device_tpm_sts_read.1242483567 |
|
|
May 26 01:51:54 AM PDT 23 |
May 26 01:51:55 AM PDT 23 |
197161108 ps |
| T164 |
/workspace/coverage/default/19.spi_device_txrx.276965318 |
|
|
May 26 01:53:56 AM PDT 23 |
May 26 01:57:32 AM PDT 23 |
388504047180 ps |
| T165 |
/workspace/coverage/default/9.spi_device_extreme_fifo_size.894487407 |
|
|
May 26 01:51:47 AM PDT 23 |
May 26 02:34:30 AM PDT 23 |
165250062993 ps |
| T103 |
/workspace/coverage/default/25.spi_device_tpm_sts_read.928322242 |
|
|
May 26 01:55:07 AM PDT 23 |
May 26 01:55:08 AM PDT 23 |
18738858 ps |
| T59 |
/workspace/coverage/default/9.spi_device_abort.1934567733 |
|
|
May 26 01:51:48 AM PDT 23 |
May 26 01:51:49 AM PDT 23 |
17224906 ps |
| T166 |
/workspace/coverage/default/24.spi_device_pass_cmd_filtering.205875023 |
|
|
May 26 01:54:46 AM PDT 23 |
May 26 01:54:52 AM PDT 23 |
1240692143 ps |
| T149 |
/workspace/coverage/default/38.spi_device_intr.1028942375 |
|
|
May 26 01:57:36 AM PDT 23 |
May 26 01:57:52 AM PDT 23 |
3462617001 ps |
| T20 |
/workspace/coverage/default/44.spi_device_stress_all.295680290 |
|
|
May 26 01:59:10 AM PDT 23 |
May 26 02:26:35 AM PDT 23 |
394080047261 ps |
| T53 |
/workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.342722697 |
|
|
May 26 01:50:36 AM PDT 23 |
May 26 01:51:45 AM PDT 23 |
8634173871 ps |
| T52 |
/workspace/coverage/default/22.spi_device_abort.1036489109 |
|
|
May 26 01:54:40 AM PDT 23 |
May 26 01:54:41 AM PDT 23 |
15983008 ps |
| T213 |
/workspace/coverage/default/7.spi_device_cfg_cmd.94178427 |
|
|
May 26 01:50:36 AM PDT 23 |
May 26 01:50:39 AM PDT 23 |
63066910 ps |
| T260 |
/workspace/coverage/default/49.spi_device_intercept.2300567749 |
|
|
May 26 02:00:18 AM PDT 23 |
May 26 02:00:24 AM PDT 23 |
1585908642 ps |
| T379 |
/workspace/coverage/default/7.spi_device_tpm_sts_read.464936012 |
|
|
May 26 01:50:50 AM PDT 23 |
May 26 01:50:51 AM PDT 23 |
93962135 ps |
| T505 |
/workspace/coverage/default/25.spi_device_byte_transfer.3941283912 |
|
|
May 26 01:54:45 AM PDT 23 |
May 26 01:54:48 AM PDT 23 |
120604417 ps |
| T506 |
/workspace/coverage/default/28.spi_device_perf.157640253 |
|
|
May 26 01:55:44 AM PDT 23 |
May 26 02:02:54 AM PDT 23 |
65294302728 ps |
| T507 |
/workspace/coverage/default/18.spi_device_rx_timeout.4255927421 |
|
|
May 26 01:53:52 AM PDT 23 |
May 26 01:53:58 AM PDT 23 |
1666640830 ps |