SPI_DEVICE Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	0.920s	37.422us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.330s	53.422us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.070s	109.761us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.190s	2.385ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.760s	1.308ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.190s	53.154us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.070s	109.761us	20	20	100.00
		spi_device_csr_aliasing	18.760s	1.308ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	9.840s	792.202us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	5.060s	242.795us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	4.701m	45.776ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	13.524m	69.486ms	50	50	100.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	4.435m	39.287ms	50	50	100.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	4.271m	52.275ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	4.271m	52.275ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.830s	23.583us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	0.960s	46.761us	50	50	100.00
V2	interrupts	spi_device_intr	33.620s	9.118ms	50	50	100.00
V2	abort	spi_device_abort	0.800s	21.440us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.510s	272.581us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	6.570s	1.222ms	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	2.960s	399.473us	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	14.534m	113.593ms	50	50	100.00
V2	perf	spi_device_perf	2.598m	8.265ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.830s	29.083us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.060s	40.065us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	19.940us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	3.150s	334.616us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	3.150s	334.616us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.220s	12.597ms	50	50	100.00
		spi_device_tpm_sts_read	1.270s	154.475us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.207m	14.078ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	26.490s	11.601ms	50	50	100.00
		spi_device_flash_all	4.876m	85.193ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	41.750s	18.486ms	50	50	100.00
		spi_device_flash_all	4.876m	85.193ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	41.750s	18.486ms	50	50	100.00
		spi_device_flash_all	4.876m	85.193ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	4.876m	85.193ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	9.660s	3.388ms	50	50	100.00
		spi_device_flash_all	4.876m	85.193ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	9.660s	3.388ms	50	50	100.00
		spi_device_flash_all	4.876m	85.193ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	9.660s	3.388ms	50	50	100.00
		spi_device_flash_all	4.876m	85.193ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	9.660s	3.388ms	50	50	100.00
		spi_device_flash_all	4.876m	85.193ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	17.500s	6.582ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	48.700s	22.218ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	48.700s	22.218ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	48.700s	22.218ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	8.840s	1.087ms	50	50	100.00
		spi_device_read_buffer_direct	4.260s	293.866us	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	48.700s	22.218ms	50	50	100.00
		spi_device_flash_all	4.876m	85.193ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	4.876m	85.193ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	4.876m	85.193ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	7.040s	1.983ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	7.040s	1.983ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.884m	166.164ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.971m	97.013ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.561m	117.643ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.760s	17.994us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.780s	22.136us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.110s	235.635us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.110s	235.635us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.330s	53.422us	5	5	100.00
		spi_device_csr_rw	2.070s	109.761us	20	20	100.00
		spi_device_csr_aliasing	18.760s	1.308ms	5	5	100.00
		spi_device_same_csr_outstanding	3.620s	214.206us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.330s	53.422us	5	5	100.00
		spi_device_csr_rw	2.070s	109.761us	20	20	100.00
		spi_device_csr_aliasing	18.760s	1.308ms	5	5	100.00
		spi_device_same_csr_outstanding	3.620s	214.206us	20	20	100.00
V2		TOTAL			1680	1680	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.120s	101.743us	5	5	100.00
		spi_device_tl_intg_err	14.650s	942.254us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.650s	942.254us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1820	1820	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	36	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.61	98.96	95.60	98.63	92.06	97.97	87.00	78.04

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