Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	425	1			T2	1		T3	11		T9	1
all_values[1]	425	1			T2	1		T3	11		T9	1
all_values[2]	425	1			T2	1		T3	11		T9	1
all_values[3]	425	1			T2	1		T3	11		T9	1
all_values[4]	425	1			T2	1		T3	11		T9	1
all_values[5]	425	1			T2	1		T3	11		T9	1
all_values[6]	425	1			T2	1		T3	11		T9	1
all_values[7]	425	1			T2	1		T3	11		T9	1
all_values[8]	425	1			T2	1		T3	11		T9	1
all_values[9]	425	1			T2	1		T3	11		T9	1
all_values[10]	425	1			T2	1		T3	11		T9	1
all_values[11]	425	1			T2	1		T3	11		T9	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2623

1

T2

12

T3

68

T9

12

auto[1]

2477

1

T3

64

T7

34

T8

72

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3131

1

T2

12

T3

82

T9

12

auto[1]

1969

1

T3

50

T7

8

T8

45

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	151	1			T2	1		T3	5		T9	1
all_values[0]	auto[0]	auto[1]	65	1			T3	1		T8	1		T14	6
all_values[0]	auto[1]	auto[0]	122	1			T3	3		T7	3		T8	3
all_values[0]	auto[1]	auto[1]	87	1			T3	2		T8	4		T13	2
all_values[1]	auto[0]	auto[0]	143	1			T2	1		T3	2		T9	1
all_values[1]	auto[0]	auto[1]	71	1			T3	4		T8	4		T14	3
all_values[1]	auto[1]	auto[0]	132	1			T3	5		T7	4		T8	1
all_values[1]	auto[1]	auto[1]	79	1			T8	2		T14	2		T28	1
all_values[2]	auto[0]	auto[0]	152	1			T2	1		T9	1		T7	3
all_values[2]	auto[0]	auto[1]	90	1			T3	5		T8	1		T13	2
all_values[2]	auto[1]	auto[0]	96	1			T3	4		T7	1		T8	4
all_values[2]	auto[1]	auto[1]	87	1			T3	2		T7	1		T13	1
all_values[3]	auto[0]	auto[0]	141	1			T2	1		T3	8		T9	1
all_values[3]	auto[0]	auto[1]	83	1			T3	3		T8	2		T14	1
all_values[3]	auto[1]	auto[0]	120	1			T7	2		T8	4		T13	1
all_values[3]	auto[1]	auto[1]	81	1			T7	2		T8	3		T14	4
all_values[4]	auto[0]	auto[0]	134	1			T2	1		T3	5		T9	1
all_values[4]	auto[0]	auto[1]	84	1			T3	2		T7	1		T8	2
all_values[4]	auto[1]	auto[0]	103	1			T3	2		T7	2		T8	2
all_values[4]	auto[1]	auto[1]	104	1			T3	2		T7	2		T8	3
all_values[5]	auto[0]	auto[0]	127	1			T2	1		T9	1		T8	3
all_values[5]	auto[0]	auto[1]	82	1			T3	2		T7	1		T14	2
all_values[5]	auto[1]	auto[0]	126	1			T3	2		T7	4		T8	5
all_values[5]	auto[1]	auto[1]	90	1			T3	7		T8	3		T14	1
all_values[6]	auto[0]	auto[0]	115	1			T2	1		T3	3		T9	1
all_values[6]	auto[0]	auto[1]	70	1			T8	2		T14	5		T28	6
all_values[6]	auto[1]	auto[0]	132	1			T3	7		T8	5		T13	2
all_values[6]	auto[1]	auto[1]	108	1			T3	1		T8	2		T13	2
all_values[7]	auto[0]	auto[0]	151	1			T2	1		T3	4		T9	1
all_values[7]	auto[0]	auto[1]	66	1			T3	4		T14	3		T28	3
all_values[7]	auto[1]	auto[0]	120	1			T3	2		T7	2		T8	4
all_values[7]	auto[1]	auto[1]	88	1			T3	1		T8	4		T14	2
all_values[8]	auto[0]	auto[0]	138	1			T2	1		T3	2		T9	1
all_values[8]	auto[0]	auto[1]	76	1			T3	1		T8	2		T14	3
all_values[8]	auto[1]	auto[0]	134	1			T3	7		T7	4		T8	4
all_values[8]	auto[1]	auto[1]	77	1			T3	1		T13	1		T14	2
all_values[9]	auto[0]	auto[0]	155	1			T2	1		T3	5		T9	1
all_values[9]	auto[0]	auto[1]	74	1			T3	1		T13	1		T14	1
all_values[9]	auto[1]	auto[0]	104	1			T3	2		T7	2		T8	6
all_values[9]	auto[1]	auto[1]	92	1			T3	3		T8	2		T13	3
all_values[10]	auto[0]	auto[0]	129	1			T2	1		T3	3		T9	1
all_values[10]	auto[0]	auto[1]	91	1			T3	2		T8	1		T13	1
all_values[10]	auto[1]	auto[0]	128	1			T3	5		T8	6		T13	1
all_values[10]	auto[1]	auto[1]	77	1			T3	1		T8	2		T13	3
all_values[11]	auto[0]	auto[0]	158	1			T2	1		T3	3		T9	1
all_values[11]	auto[0]	auto[1]	77	1			T3	3		T8	2		T13	2
all_values[11]	auto[1]	auto[0]	120	1			T3	3		T7	4		T14	5
all_values[11]	auto[1]	auto[1]	70	1			T3	2		T7	1		T8	3