Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
60.02	71.17	76.17	75.34	0.00	77.00	100.00	20.49

Total tests in report: 175

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
50.91	50.91	69.80	69.80	70.16	70.16	54.33	54.33	0.00	0.00	74.94	74.94	81.07	81.07	6.10	6.10	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.49090447
56.60	5.69	69.80	0.00	72.28	2.12	80.18	25.85	0.00	0.00	75.07	0.14	91.82	10.74	7.05	0.95	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3261849553
58.78	2.18	70.03	0.23	72.82	0.55	85.88	5.69	0.00	0.00	75.07	0.00	91.82	0.00	15.82	8.77	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.908628554
60.62	1.84	71.09	1.06	75.17	2.35	86.79	0.91	0.00	0.00	76.99	1.91	97.44	5.63	16.87	1.05	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4270751002
61.15	0.53	71.17	0.07	76.05	0.88	87.24	0.46	0.00	0.00	77.00	0.02	98.21	0.77	18.39	1.52	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.913259243
61.41	0.26	71.17	0.00	76.05	0.00	87.24	0.00	0.00	0.00	77.00	0.00	100.00	1.79	18.44	0.05	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.912729754
61.67	0.26	71.17	0.00	76.05	0.00	87.70	0.46	0.00	0.00	77.00	0.00	100.00	0.00	19.77	1.33	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.406770228
61.71	0.04	71.17	0.00	76.05	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.06	0.29	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.2255453016
61.75	0.04	71.17	0.00	76.05	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.34	0.29	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3732469936
61.77	0.01	71.17	0.00	76.15	0.10	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.34	0.00	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2146808135
61.77	0.01	71.17	0.00	76.15	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.39	0.05	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3913006522
61.78	0.01	71.17	0.00	76.15	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.44	0.05	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1540737434
61.79	0.01	71.17	0.00	76.15	0.00	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.49	0.05	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1037503954
61.79	0.01	71.17	0.00	76.17	0.03	87.70	0.00	0.00	0.00	77.00	0.00	100.00	0.00	20.49	0.00	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3329827347

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1684193578
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1739268414
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3291134629
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2059863974
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3592413257
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3913543187
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.671524531
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1706317507
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4293197839
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3970898751
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.644404116
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1207544124
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1110497311
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1899021232
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4158990411
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3332453496
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.117220582
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3645651769
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2759351838
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3750097645
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.4293403259
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.929650445
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3128221775
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2812815214
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1563229798
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.2116852676
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3557193384
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3927819098
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1494851209
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2488248333
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2336111310
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2287526712
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2269905269
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4255610999
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3951223954
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1875030367
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.2625552527
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3357243323
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3823093994
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.641221072
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2515785516
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2964060234
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.693341108
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2994168485
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1612775713
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.488285865
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.356442356
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.1267053403
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1957536026
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3408882928
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.24425452
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.742251860
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.2924128881
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.285491424
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4262009385
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.590415047
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.702324193
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3711348684
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2103584183
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.59376827
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.713285389
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.3722251930
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1944400437
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1833327659
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.768159880
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1952449263
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1960723259
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2093648577
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1864876962
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3575480171
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3019333299
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3444801111
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1757133938
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3024858519
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1901611623
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.2432079131
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3143915526
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2034569713
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3726674067
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3719850930
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4185841436
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.3221215044
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.4281658416
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.3719742990
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.1084592449
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3142597286
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.658026897
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.2007479521
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.1726220206
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.4273468858
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.3969925127
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4011612886
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2341322998
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3025416982
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4200538405
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.276170767
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.4158127211
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3185057589
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4174154732
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.748954535
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2176689151
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3402331828
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.3393319395
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.1538898799
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.565219821
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.1698987620
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.3818532506
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.4117052716
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.202775452
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.4216199776
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.1161903557
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.2459940880
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3035406609
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.428272440
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2008191097
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4064111365
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.978237449
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.1565761734
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1236112426
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1510010052
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.931065091
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2144698676
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2912590053
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.1363463403
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.4223599537
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.3419869278
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.3887139203
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.2584930034
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.1114444936
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3263538421
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.3434586143
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.2252674987
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.552531965
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3226033823
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.1394191079
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4143806008
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3727607420
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2673438760
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1341058317
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3837045169
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.157488197
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3718126895
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2706002169
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4235475418
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4017478989
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.816991097
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2180130723
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3890054419
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3872255390
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3664556931
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2756066633
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.3849366024
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1779406315
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2532823359
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1838040111
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2217806632
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3165185
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.579585546
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3713783177
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2329509824
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1491990395

Total test records in report: 175

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.49090447	Dec 20 12:34:05 PM PST 23	Dec 20 12:34:18 PM PST 23	92600824 ps
T2	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.913259243	Dec 20 12:32:30 PM PST 23	Dec 20 12:33:16 PM PST 23	483505028 ps
T3	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.908628554	Dec 20 12:32:28 PM PST 23	Dec 20 12:33:12 PM PST 23	229486784 ps
T9	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2176689151	Dec 20 12:34:28 PM PST 23	Dec 20 12:34:33 PM PST 23	174662119 ps
T7	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.1726220206	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:16 PM PST 23	24304590 ps
T8	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.1538898799	Dec 20 12:34:34 PM PST 23	Dec 20 12:34:43 PM PST 23	54662464 ps
T13	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.4223599537	Dec 20 12:33:06 PM PST 23	Dec 20 12:33:56 PM PST 23	16286226 ps
T4	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3664556931	Dec 20 12:33:05 PM PST 23	Dec 20 12:33:56 PM PST 23	12445511 ps
T14	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.2007479521	Dec 20 12:32:36 PM PST 23	Dec 20 12:33:21 PM PST 23	82489113 ps
T5	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4064111365	Dec 20 12:32:26 PM PST 23	Dec 20 12:33:09 PM PST 23	21914926 ps
T15	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1236112426	Dec 20 12:32:28 PM PST 23	Dec 20 12:33:13 PM PST 23	77964305 ps
T25	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2756066633	Dec 20 12:32:35 PM PST 23	Dec 20 12:33:19 PM PST 23	60284321 ps
T6	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3261849553	Dec 20 12:32:39 PM PST 23	Dec 20 12:33:25 PM PST 23	34281790 ps
T16	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2034569713	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:19 PM PST 23	935986335 ps
T28	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.2252674987	Dec 20 12:32:42 PM PST 23	Dec 20 12:33:26 PM PST 23	16611780 ps
T10	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4270751002	Dec 20 12:32:52 PM PST 23	Dec 20 12:33:48 PM PST 23	792754481 ps
T11	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4185841436	Dec 20 12:32:39 PM PST 23	Dec 20 12:33:29 PM PST 23	236392582 ps
T12	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1494851209	Dec 20 12:32:33 PM PST 23	Dec 20 12:33:25 PM PST 23	517936190 ps
T17	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.488285865	Dec 20 12:34:10 PM PST 23	Dec 20 12:34:19 PM PST 23	45267531 ps
T18	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3890054419	Dec 20 12:34:12 PM PST 23	Dec 20 12:34:24 PM PST 23	299345296 ps
T29	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1957536026	Dec 20 12:32:24 PM PST 23	Dec 20 12:33:09 PM PST 23	49240095 ps
T44	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.202775452	Dec 20 12:34:12 PM PST 23	Dec 20 12:34:19 PM PST 23	15377299 ps
T30	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2008191097	Dec 20 12:32:56 PM PST 23	Dec 20 12:33:46 PM PST 23	60049919 ps
T19	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.671524531	Dec 20 12:33:00 PM PST 23	Dec 20 12:33:58 PM PST 23	447275364 ps
T56	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.2255453016	Dec 20 12:34:06 PM PST 23	Dec 20 12:34:18 PM PST 23	69529350 ps
T60	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.406770228	Dec 20 12:32:57 PM PST 23	Dec 20 12:33:47 PM PST 23	41610675 ps
T31	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.912729754	Dec 20 12:32:33 PM PST 23	Dec 20 12:33:19 PM PST 23	136290257 ps
T57	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.1565761734	Dec 20 12:32:29 PM PST 23	Dec 20 12:33:12 PM PST 23	49293969 ps
T26	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1838040111	Dec 20 12:32:54 PM PST 23	Dec 20 12:33:55 PM PST 23	271403842 ps
T43	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2180130723	Dec 20 12:32:37 PM PST 23	Dec 20 12:33:24 PM PST 23	241503980 ps
T32	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1706317507	Dec 20 12:32:34 PM PST 23	Dec 20 12:33:18 PM PST 23	249068293 ps
T61	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.3434586143	Dec 20 12:32:27 PM PST 23	Dec 20 12:33:10 PM PST 23	13350332 ps
T20	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3128221775	Dec 20 12:32:37 PM PST 23	Dec 20 12:33:23 PM PST 23	121400949 ps
T58	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.3969925127	Dec 20 12:32:26 PM PST 23	Dec 20 12:33:09 PM PST 23	53384497 ps
T21	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3719850930	Dec 20 12:33:55 PM PST 23	Dec 20 12:34:17 PM PST 23	29741385 ps
T69	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.1084592449	Dec 20 12:32:27 PM PST 23	Dec 20 12:33:11 PM PST 23	39183807 ps
T33	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2964060234	Dec 20 12:34:11 PM PST 23	Dec 20 12:34:20 PM PST 23	102664468 ps
T22	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3402331828	Dec 20 12:32:23 PM PST 23	Dec 20 12:33:28 PM PST 23	931278931 ps
T54	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3024858519	Dec 20 12:32:37 PM PST 23	Dec 20 12:33:22 PM PST 23	38393635 ps
T55	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.3719742990	Dec 20 12:32:25 PM PST 23	Dec 20 12:33:09 PM PST 23	34953238 ps
T70	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.1161903557	Dec 20 12:32:25 PM PST 23	Dec 20 12:33:08 PM PST 23	57885906 ps
T71	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.3722251930	Dec 20 12:32:52 PM PST 23	Dec 20 12:33:40 PM PST 23	12292919 ps
T72	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.1363463403	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:15 PM PST 23	18642543 ps
T34	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1875030367	Dec 20 12:32:51 PM PST 23	Dec 20 12:33:40 PM PST 23	164141256 ps
T27	/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.768159880	Dec 20 12:32:52 PM PST 23	Dec 20 12:33:46 PM PST 23	163921183 ps
T23	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3872255390	Dec 20 12:34:11 PM PST 23	Dec 20 12:34:40 PM PST 23	4423689461 ps
T24	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1864876962	Dec 20 12:33:04 PM PST 23	Dec 20 12:33:56 PM PST 23	315317531 ps
T73	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3291134629	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:16 PM PST 23	51792955 ps
T35	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4143806008	Dec 20 12:32:43 PM PST 23	Dec 20 12:33:30 PM PST 23	1242894516 ps
T74	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3142597286	Dec 20 12:32:29 PM PST 23	Dec 20 12:33:13 PM PST 23	49222480 ps
T36	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.590415047	Dec 20 12:32:37 PM PST 23	Dec 20 12:33:24 PM PST 23	38583794 ps
T37	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1901611623	Dec 20 12:32:26 PM PST 23	Dec 20 12:33:11 PM PST 23	138030358 ps
T38	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.356442356	Dec 20 12:34:11 PM PST 23	Dec 20 12:34:21 PM PST 23	102922326 ps
T75	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.3393319395	Dec 20 12:34:34 PM PST 23	Dec 20 12:34:43 PM PST 23	60524269 ps
T39	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3970898751	Dec 20 12:34:11 PM PST 23	Dec 20 12:34:43 PM PST 23	1260274704 ps
T76	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.3849366024	Dec 20 12:32:34 PM PST 23	Dec 20 12:33:17 PM PST 23	55021133 ps
T62	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.285491424	Dec 20 12:34:11 PM PST 23	Dec 20 12:34:30 PM PST 23	830437128 ps
T40	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3913543187	Dec 20 12:32:33 PM PST 23	Dec 20 12:33:22 PM PST 23	170707658 ps
T77	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.3818532506	Dec 20 12:34:34 PM PST 23	Dec 20 12:34:43 PM PST 23	39697795 ps
T49	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3645651769	Dec 20 12:32:32 PM PST 23	Dec 20 12:33:23 PM PST 23	347751695 ps
T78	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1037503954	Dec 20 12:32:29 PM PST 23	Dec 20 12:33:13 PM PST 23	15420589 ps
T53	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1110497311	Dec 20 12:32:41 PM PST 23	Dec 20 12:33:26 PM PST 23	44729056 ps
T79	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.4158127211	Dec 20 12:34:28 PM PST 23	Dec 20 12:34:29 PM PST 23	30217004 ps
T41	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3185057589	Dec 20 12:32:39 PM PST 23	Dec 20 12:33:25 PM PST 23	279012666 ps
T80	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3035406609	Dec 20 12:32:23 PM PST 23	Dec 20 12:33:21 PM PST 23	1160079811 ps
T81	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.157488197	Dec 20 12:34:34 PM PST 23	Dec 20 12:34:43 PM PST 23	20087044 ps
T82	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3726674067	Dec 20 12:34:11 PM PST 23	Dec 20 12:34:20 PM PST 23	300351193 ps
T83	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.816991097	Dec 20 12:34:11 PM PST 23	Dec 20 12:34:19 PM PST 23	12517129 ps
T84	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1952449263	Dec 20 12:32:50 PM PST 23	Dec 20 12:33:38 PM PST 23	43605490 ps
T50	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1944400437	Dec 20 12:33:06 PM PST 23	Dec 20 12:33:59 PM PST 23	346435106 ps
T45	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2144698676	Dec 20 12:32:36 PM PST 23	Dec 20 12:33:22 PM PST 23	191574782 ps
T85	/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2812815214	Dec 20 12:32:25 PM PST 23	Dec 20 12:33:09 PM PST 23	40831850 ps
T42	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3329827347	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:17 PM PST 23	25290475 ps
T86	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4158990411	Dec 20 12:32:35 PM PST 23	Dec 20 12:33:21 PM PST 23	95089445 ps
T87	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.2924128881	Dec 20 12:32:54 PM PST 23	Dec 20 12:33:42 PM PST 23	12808513 ps
T88	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.658026897	Dec 20 12:32:30 PM PST 23	Dec 20 12:33:13 PM PST 23	14809167 ps
T51	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2673438760	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:36 PM PST 23	1118075502 ps
T89	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2759351838	Dec 20 12:32:37 PM PST 23	Dec 20 12:33:22 PM PST 23	49525792 ps
T47	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1833327659	Dec 20 12:34:01 PM PST 23	Dec 20 12:34:19 PM PST 23	49174259 ps
T48	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2146808135	Dec 20 12:32:32 PM PST 23	Dec 20 12:33:20 PM PST 23	2446951475 ps
T90	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4174154732	Dec 20 12:32:29 PM PST 23	Dec 20 12:33:20 PM PST 23	139110696 ps
T91	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3951223954	Dec 20 12:32:37 PM PST 23	Dec 20 12:33:21 PM PST 23	37329269 ps
T92	/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2515785516	Dec 20 12:32:38 PM PST 23	Dec 20 12:33:24 PM PST 23	40954233 ps
T93	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2269905269	Dec 20 12:32:41 PM PST 23	Dec 20 12:33:28 PM PST 23	595546397 ps
T52	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2093648577	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:16 PM PST 23	84788374 ps
T94	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.3221215044	Dec 20 12:32:35 PM PST 23	Dec 20 12:33:18 PM PST 23	20903486 ps
T63	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3732469936	Dec 20 12:34:34 PM PST 23	Dec 20 12:35:00 PM PST 23	1187140817 ps
T59	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.693341108	Dec 20 12:33:55 PM PST 23	Dec 20 12:34:18 PM PST 23	565553578 ps
T66	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.641221072	Dec 20 12:32:46 PM PST 23	Dec 20 12:33:48 PM PST 23	1103752759 ps
T95	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.644404116	Dec 20 12:32:47 PM PST 23	Dec 20 12:34:11 PM PST 23	6238513339 ps
T96	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2059863974	Dec 20 12:32:41 PM PST 23	Dec 20 12:33:27 PM PST 23	39853056 ps
T64	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1612775713	Dec 20 12:32:52 PM PST 23	Dec 20 12:33:52 PM PST 23	210643676 ps
T97	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2341322998	Dec 20 12:32:38 PM PST 23	Dec 20 12:33:46 PM PST 23	2775046136 ps
T98	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.4293403259	Dec 20 12:32:28 PM PST 23	Dec 20 12:33:11 PM PST 23	15511283 ps
T99	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.1267053403	Dec 20 12:32:39 PM PST 23	Dec 20 12:33:24 PM PST 23	12915138 ps
T100	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3711348684	Dec 20 12:32:35 PM PST 23	Dec 20 12:33:22 PM PST 23	64156001 ps
T101	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3408882928	Dec 20 12:34:11 PM PST 23	Dec 20 12:34:23 PM PST 23	199854034 ps
T102	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4235475418	Dec 20 12:32:42 PM PST 23	Dec 20 12:33:26 PM PST 23	98408200 ps
T103	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.2116852676	Dec 20 12:32:24 PM PST 23	Dec 20 12:33:06 PM PST 23	12381266 ps
T104	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3718126895	Dec 20 12:32:58 PM PST 23	Dec 20 12:33:48 PM PST 23	79547265 ps
T105	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2287526712	Dec 20 12:32:30 PM PST 23	Dec 20 12:33:14 PM PST 23	53452765 ps
T106	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1684193578	Dec 20 12:32:26 PM PST 23	Dec 20 12:33:18 PM PST 23	274584674 ps
T107	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.4273468858	Dec 20 12:32:30 PM PST 23	Dec 20 12:33:13 PM PST 23	13746354 ps
T108	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2706002169	Dec 20 12:32:39 PM PST 23	Dec 20 12:33:27 PM PST 23	436113894 ps
T109	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2103584183	Dec 20 12:32:37 PM PST 23	Dec 20 12:33:24 PM PST 23	219989288 ps
T65	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2912590053	Dec 20 12:32:21 PM PST 23	Dec 20 12:33:10 PM PST 23	602349283 ps
T110	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.24425452	Dec 20 12:34:11 PM PST 23	Dec 20 12:34:33 PM PST 23	693459145 ps
T111	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.748954535	Dec 20 12:32:39 PM PST 23	Dec 20 12:33:27 PM PST 23	68576688 ps
T112	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3823093994	Dec 20 12:32:30 PM PST 23	Dec 20 12:33:14 PM PST 23	43661986 ps
T113	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.4281658416	Dec 20 12:32:27 PM PST 23	Dec 20 12:33:10 PM PST 23	31688929 ps
T114	/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.713285389	Dec 20 12:32:52 PM PST 23	Dec 20 12:33:41 PM PST 23	152913498 ps
T115	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3592413257	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:15 PM PST 23	17570333 ps
T46	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1207544124	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:16 PM PST 23	23218069 ps
T116	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.978237449	Dec 20 12:32:26 PM PST 23	Dec 20 12:33:12 PM PST 23	37620892 ps
T117	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4293197839	Dec 20 12:32:27 PM PST 23	Dec 20 12:33:15 PM PST 23	353221593 ps
T118	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.552531965	Dec 20 12:34:35 PM PST 23	Dec 20 12:34:54 PM PST 23	22245313 ps
T119	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.428272440	Dec 20 12:32:25 PM PST 23	Dec 20 12:33:48 PM PST 23	8330184428 ps
T120	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1510010052	Dec 20 12:32:27 PM PST 23	Dec 20 12:33:16 PM PST 23	456342155 ps
T121	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2488248333	Dec 20 12:32:35 PM PST 23	Dec 20 12:33:20 PM PST 23	65136938 ps
T122	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.2459940880	Dec 20 12:32:45 PM PST 23	Dec 20 12:33:30 PM PST 23	35420670 ps
T123	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3727607420	Dec 20 12:32:33 PM PST 23	Dec 20 12:33:20 PM PST 23	64298022 ps
T124	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.1394191079	Dec 20 12:32:33 PM PST 23	Dec 20 12:33:17 PM PST 23	38603281 ps
T125	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3575480171	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:23 PM PST 23	294037648 ps
T126	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.1114444936	Dec 20 12:32:45 PM PST 23	Dec 20 12:33:30 PM PST 23	35593843 ps
T127	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2217806632	Dec 20 12:32:32 PM PST 23	Dec 20 12:33:18 PM PST 23	71777307 ps
T128	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3837045169	Dec 20 12:32:36 PM PST 23	Dec 20 12:33:22 PM PST 23	886838189 ps
T129	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4262009385	Dec 20 12:34:29 PM PST 23	Dec 20 12:34:32 PM PST 23	112498909 ps
T130	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.2625552527	Dec 20 12:32:40 PM PST 23	Dec 20 12:33:23 PM PST 23	55496460 ps
T131	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1960723259	Dec 20 12:33:04 PM PST 23	Dec 20 12:33:55 PM PST 23	82904801 ps
T132	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3019333299	Dec 20 12:32:35 PM PST 23	Dec 20 12:33:27 PM PST 23	2122294882 ps
T133	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3263538421	Dec 20 12:32:41 PM PST 23	Dec 20 12:33:25 PM PST 23	13675996 ps
T134	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1563229798	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:16 PM PST 23	51224362 ps
T135	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.276170767	Dec 20 12:34:16 PM PST 23	Dec 20 12:34:22 PM PST 23	149552640 ps
T136	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3332453496	Dec 20 12:34:35 PM PST 23	Dec 20 12:34:47 PM PST 23	758726330 ps
T137	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1739268414	Dec 20 12:32:41 PM PST 23	Dec 20 12:34:01 PM PST 23	7675345566 ps
T138	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2994168485	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:17 PM PST 23	129730169 ps
T139	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.3419869278	Dec 20 12:34:11 PM PST 23	Dec 20 12:34:19 PM PST 23	19724390 ps
T140	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.117220582	Dec 20 12:32:47 PM PST 23	Dec 20 12:33:35 PM PST 23	1352392199 ps
T141	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3143915526	Dec 20 12:32:39 PM PST 23	Dec 20 12:33:26 PM PST 23	36017017 ps
T142	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.4216199776	Dec 20 12:32:30 PM PST 23	Dec 20 12:33:13 PM PST 23	11356137 ps
T143	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1899021232	Dec 20 12:32:28 PM PST 23	Dec 20 12:33:12 PM PST 23	31091525 ps
T144	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.742251860	Dec 20 12:33:01 PM PST 23	Dec 20 12:33:52 PM PST 23	51153983 ps
T145	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.579585546	Dec 20 12:32:38 PM PST 23	Dec 20 12:33:22 PM PST 23	43670858 ps
T146	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.4117052716	Dec 20 12:34:35 PM PST 23	Dec 20 12:34:43 PM PST 23	48209348 ps
T67	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4255610999	Dec 20 12:33:01 PM PST 23	Dec 20 12:34:03 PM PST 23	821691383 ps
T147	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.3887139203	Dec 20 12:32:46 PM PST 23	Dec 20 12:33:31 PM PST 23	51929406 ps
T148	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2336111310	Dec 20 12:32:35 PM PST 23	Dec 20 12:33:19 PM PST 23	150804314 ps
T149	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.2432079131	Dec 20 12:32:38 PM PST 23	Dec 20 12:33:22 PM PST 23	15514254 ps
T150	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.565219821	Dec 20 12:32:39 PM PST 23	Dec 20 12:33:23 PM PST 23	46486259 ps
T151	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3025416982	Dec 20 12:34:16 PM PST 23	Dec 20 12:34:21 PM PST 23	24616763 ps
T152	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.1698987620	Dec 20 12:32:54 PM PST 23	Dec 20 12:33:43 PM PST 23	42350431 ps
T153	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.931065091	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:16 PM PST 23	75405298 ps
T154	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3226033823	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:16 PM PST 23	41096295 ps
T155	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4017478989	Dec 20 12:33:55 PM PST 23	Dec 20 12:34:17 PM PST 23	95899781 ps
T156	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3927819098	Dec 20 12:32:28 PM PST 23	Dec 20 12:33:14 PM PST 23	53042465 ps
T157	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1341058317	Dec 20 12:34:12 PM PST 23	Dec 20 12:34:19 PM PST 23	72683819 ps
T158	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3713783177	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:18 PM PST 23	319032239 ps
T159	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1779406315	Dec 20 12:32:30 PM PST 23	Dec 20 12:33:15 PM PST 23	160309621 ps
T68	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3913006522	Dec 20 12:32:22 PM PST 23	Dec 20 12:33:18 PM PST 23	707973499 ps
T160	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1757133938	Dec 20 12:32:35 PM PST 23	Dec 20 12:33:20 PM PST 23	107933193 ps
T161	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3444801111	Dec 20 12:32:38 PM PST 23	Dec 20 12:33:46 PM PST 23	434549086 ps
T162	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1491990395	Dec 20 12:33:14 PM PST 23	Dec 20 12:34:09 PM PST 23	1322639037 ps
T163	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4011612886	Dec 20 12:32:28 PM PST 23	Dec 20 12:33:20 PM PST 23	1475342908 ps
T164	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1540737434	Dec 20 12:32:36 PM PST 23	Dec 20 12:33:38 PM PST 23	1207932189 ps
T165	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2329509824	Dec 20 12:34:28 PM PST 23	Dec 20 12:34:33 PM PST 23	350389814 ps
T166	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3165185	Dec 20 12:32:46 PM PST 23	Dec 20 12:33:33 PM PST 23	189777474 ps
T167	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3750097645	Dec 20 12:32:27 PM PST 23	Dec 20 12:33:12 PM PST 23	31569719 ps
T168	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.59376827	Dec 20 12:32:54 PM PST 23	Dec 20 12:33:43 PM PST 23	27666064 ps
T169	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2532823359	Dec 20 12:32:27 PM PST 23	Dec 20 12:33:17 PM PST 23	4636848938 ps
T170	/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4200538405	Dec 20 12:33:06 PM PST 23	Dec 20 12:33:57 PM PST 23	16501051 ps
T171	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.702324193	Dec 20 12:34:05 PM PST 23	Dec 20 12:34:17 PM PST 23	46110169 ps
T172	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3357243323	Dec 20 12:32:25 PM PST 23	Dec 20 12:33:10 PM PST 23	283270361 ps
T173	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3557193384	Dec 20 12:32:31 PM PST 23	Dec 20 12:33:17 PM PST 23	45937070 ps
T174	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.929650445	Dec 20 12:32:57 PM PST 23	Dec 20 12:33:48 PM PST 23	258829326 ps
T175	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.2584930034	Dec 20 12:34:11 PM PST 23	Dec 20 12:34:19 PM PST 23	40728066 ps

Test location	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.49090447
Short name	T1
Test name
Test status
Simulation time	92600824 ps
CPU time	1.83 seconds
Started	Dec 20 12:34:05 PM PST 23
Finished	Dec 20 12:34:18 PM PST 23
Peak memory	214452 kb
Host	smart-3871a88d-5a3d-4bba-8feb-fa9348a66407
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49090447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sp i_device_same_csr_outstanding.49090447
Directory	/workspace/16.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3261849553
Short name	T6
Test name
Test status
Simulation time	34281790 ps
CPU time	1.8 seconds
Started	Dec 20 12:32:39 PM PST 23
Finished	Dec 20 12:33:25 PM PST 23
Peak memory	218156 kb
Host	smart-a2aaa88d-10c1-4833-8c39-9597bdcb50a2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261849553 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3261849553
Directory	/workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.908628554
Short name	T3
Test name
Test status
Simulation time	229486784 ps
CPU time	0.71 seconds
Started	Dec 20 12:32:28 PM PST 23
Finished	Dec 20 12:33:12 PM PST 23
Peak memory	204812 kb
Host	smart-feb252d7-6301-4508-b461-d8992e3af5f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908628554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.908628554
Directory	/workspace/1.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4270751002
Short name	T10
Test name
Test status
Simulation time	792754481 ps
CPU time	8.15 seconds
Started	Dec 20 12:32:52 PM PST 23
Finished	Dec 20 12:33:48 PM PST 23
Peak memory	215748 kb
Host	smart-28984302-1ba9-4443-9866-93a2abd6809b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270751002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic e_tl_intg_err.4270751002
Directory	/workspace/17.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.913259243
Short name	T2
Test name
Test status
Simulation time	483505028 ps
CPU time	3.95 seconds
Started	Dec 20 12:32:30 PM PST 23
Finished	Dec 20 12:33:16 PM PST 23
Peak memory	216064 kb
Host	smart-54f7bc7f-d8a9-4d63-aaed-e54d01ca2f71
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913259243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.913259243
Directory	/workspace/16.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.912729754
Short name	T31
Test name
Test status
Simulation time	136290257 ps
CPU time	2.38 seconds
Started	Dec 20 12:32:33 PM PST 23
Finished	Dec 20 12:33:19 PM PST 23
Peak memory	207724 kb
Host	smart-ef3937e8-fdc2-4798-9c5e-cb4c5f4328bf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912729754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.912729754
Directory	/workspace/12.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.406770228
Short name	T60
Test name
Test status
Simulation time	41610675 ps
CPU time	0.71 seconds
Started	Dec 20 12:32:57 PM PST 23
Finished	Dec 20 12:33:47 PM PST 23
Peak memory	204784 kb
Host	smart-c013e8f8-ae08-46ee-bb9c-ae89cce22daa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406770228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.406770228
Directory	/workspace/40.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.2255453016
Short name	T56
Test name
Test status
Simulation time	69529350 ps
CPU time	0.79 seconds
Started	Dec 20 12:34:06 PM PST 23
Finished	Dec 20 12:34:18 PM PST 23
Peak memory	203752 kb
Host	smart-d2e8f471-5646-4479-9b99-d729d18de769
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255453016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test. 2255453016
Directory	/workspace/14.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3732469936
Short name	T63
Test name
Test status
Simulation time	1187140817 ps
CPU time	17.46 seconds
Started	Dec 20 12:34:34 PM PST 23
Finished	Dec 20 12:35:00 PM PST 23
Peak memory	215568 kb
Host	smart-19bd825c-0306-451f-8dec-bd7edf1e6265
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732469936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device _tl_intg_err.3732469936
Directory	/workspace/6.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2146808135
Short name	T48
Test name
Test status
Simulation time	2446951475 ps
CPU time	4.68 seconds
Started	Dec 20 12:32:32 PM PST 23
Finished	Dec 20 12:33:20 PM PST 23
Peak memory	216084 kb
Host	smart-7f293579-b1a2-436f-98f2-479398aa547b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146808135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2 146808135
Directory	/workspace/1.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3913006522
Short name	T68
Test name
Test status
Simulation time	707973499 ps
CPU time	14.33 seconds
Started	Dec 20 12:32:22 PM PST 23
Finished	Dec 20 12:33:18 PM PST 23
Peak memory	215944 kb
Host	smart-2dc8c3ef-398b-4122-a493-dbb3f155528c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913006522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device _tl_intg_err.3913006522
Directory	/workspace/0.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1540737434
Short name	T164
Test name
Test status
Simulation time	1207932189 ps
CPU time	17.84 seconds
Started	Dec 20 12:32:36 PM PST 23
Finished	Dec 20 12:33:38 PM PST 23
Peak memory	215752 kb
Host	smart-79b504fd-8d60-4455-865d-57cdcdc39358
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540737434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic e_tl_intg_err.1540737434
Directory	/workspace/10.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1037503954
Short name	T78
Test name
Test status
Simulation time	15420589 ps
CPU time	0.72 seconds
Started	Dec 20 12:32:29 PM PST 23
Finished	Dec 20 12:33:13 PM PST 23
Peak memory	204912 kb
Host	smart-9662ff29-8067-4327-ac6e-f1e39221b0d2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037503954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test. 1037503954
Directory	/workspace/19.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3329827347
Short name	T42
Test name
Test status
Simulation time	25290475 ps
CPU time	1.34 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:17 PM PST 23
Peak memory	215808 kb
Host	smart-095a9803-e040-4b16-ac1b-2f3e04ca55b0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329827347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_hw_reset.3329827347
Directory	/workspace/0.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1684193578
Short name	T106
Test name
Test status
Simulation time	274584674 ps
CPU time	8.58 seconds
Started	Dec 20 12:32:26 PM PST 23
Finished	Dec 20 12:33:18 PM PST 23
Peak memory	207684 kb
Host	smart-ae75ae9b-44cb-445a-9856-edc1347618de
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684193578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_aliasing.1684193578
Directory	/workspace/0.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1739268414
Short name	T137
Test name
Test status
Simulation time	7675345566 ps
CPU time	36.26 seconds
Started	Dec 20 12:32:41 PM PST 23
Finished	Dec 20 12:34:01 PM PST 23
Peak memory	215960 kb
Host	smart-ce1a69a7-2052-4baa-bb4b-6eda70760b2b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739268414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_bit_bash.1739268414
Directory	/workspace/0.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3291134629
Short name	T73
Test name
Test status
Simulation time	51792955 ps
CPU time	2.2 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:16 PM PST 23
Peak memory	219748 kb
Host	smart-47b0ce94-0d51-42ae-8025-93a0dfc08733
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291134629 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3291134629
Directory	/workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2059863974
Short name	T96
Test name
Test status
Simulation time	39853056 ps
CPU time	2.3 seconds
Started	Dec 20 12:32:41 PM PST 23
Finished	Dec 20 12:33:27 PM PST 23
Peak memory	215952 kb
Host	smart-91c22455-d01e-446b-810e-b864961544c3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059863974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2 059863974
Directory	/workspace/0.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3592413257
Short name	T115
Test name
Test status
Simulation time	17570333 ps
CPU time	0.74 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:15 PM PST 23
Peak memory	204972 kb
Host	smart-a78bf26d-1e67-4d47-aacb-d84bef4b16aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592413257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3 592413257
Directory	/workspace/0.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3913543187
Short name	T40
Test name
Test status
Simulation time	170707658 ps
CPU time	4.69 seconds
Started	Dec 20 12:32:33 PM PST 23
Finished	Dec 20 12:33:22 PM PST 23
Peak memory	215808 kb
Host	smart-fa8fd40e-3302-4bed-97bc-81213f252a78
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913543187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi _device_mem_partial_access.3913543187
Directory	/workspace/0.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.671524531
Short name	T19
Test name
Test status
Simulation time	447275364 ps
CPU time	9.16 seconds
Started	Dec 20 12:33:00 PM PST 23
Finished	Dec 20 12:33:58 PM PST 23
Peak memory	215852 kb
Host	smart-fcde1a2d-0e55-4b40-9624-9f43b73152f7
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671524531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem _walk.671524531
Directory	/workspace/0.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1706317507
Short name	T32
Test name
Test status
Simulation time	249068293 ps
CPU time	1.84 seconds
Started	Dec 20 12:32:34 PM PST 23
Finished	Dec 20 12:33:18 PM PST 23
Peak memory	215608 kb
Host	smart-1e9a420f-2bd7-412e-9f30-442be2ba6375
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706317507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s pi_device_same_csr_outstanding.1706317507
Directory	/workspace/0.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4293197839
Short name	T117
Test name
Test status
Simulation time	353221593 ps
CPU time	4.14 seconds
Started	Dec 20 12:32:27 PM PST 23
Finished	Dec 20 12:33:15 PM PST 23
Peak memory	216088 kb
Host	smart-b5d41d4f-2289-4833-b661-acafa6badd50
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293197839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4 293197839
Directory	/workspace/0.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3970898751
Short name	T39
Test name
Test status
Simulation time	1260274704 ps
CPU time	25.4 seconds
Started	Dec 20 12:34:11 PM PST 23
Finished	Dec 20 12:34:43 PM PST 23
Peak memory	207068 kb
Host	smart-704635d2-bbeb-4726-b49e-20c8d2666266
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970898751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_aliasing.3970898751
Directory	/workspace/1.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.644404116
Short name	T95
Test name
Test status
Simulation time	6238513339 ps
CPU time	38.84 seconds
Started	Dec 20 12:32:47 PM PST 23
Finished	Dec 20 12:34:11 PM PST 23
Peak memory	215704 kb
Host	smart-832cef1f-3d56-442f-9bfa-c2279bc8bd85
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644404116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr _bit_bash.644404116
Directory	/workspace/1.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1207544124
Short name	T46
Test name
Test status
Simulation time	23218069 ps
CPU time	1.38 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:16 PM PST 23
Peak memory	207688 kb
Host	smart-622385f8-1e30-44d5-8d69-b6cbb5042eb9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207544124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_hw_reset.1207544124
Directory	/workspace/1.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1110497311
Short name	T53
Test name
Test status
Simulation time	44729056 ps
CPU time	1.33 seconds
Started	Dec 20 12:32:41 PM PST 23
Finished	Dec 20 12:33:26 PM PST 23
Peak memory	217300 kb
Host	smart-7e4a6675-f79a-4c23-90e6-c1f36caefc2a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110497311 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1110497311
Directory	/workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1899021232
Short name	T143
Test name
Test status
Simulation time	31091525 ps
CPU time	1.25 seconds
Started	Dec 20 12:32:28 PM PST 23
Finished	Dec 20 12:33:12 PM PST 23
Peak memory	215908 kb
Host	smart-e0261f60-e4b7-499c-a056-14a2b3ab6b25
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899021232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1 899021232
Directory	/workspace/1.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4158990411
Short name	T86
Test name
Test status
Simulation time	95089445 ps
CPU time	2.51 seconds
Started	Dec 20 12:32:35 PM PST 23
Finished	Dec 20 12:33:21 PM PST 23
Peak memory	215704 kb
Host	smart-41895667-b705-4f2f-a02c-ca6ca3176cc0
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158990411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi _device_mem_partial_access.4158990411
Directory	/workspace/1.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3332453496
Short name	T136
Test name
Test status
Simulation time	758726330 ps
CPU time	4.74 seconds
Started	Dec 20 12:34:35 PM PST 23
Finished	Dec 20 12:34:47 PM PST 23
Peak memory	215564 kb
Host	smart-2a803f96-2e08-4bbb-878e-29d38b2a7ee8
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332453496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me m_walk.3332453496
Directory	/workspace/1.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.117220582
Short name	T140
Test name
Test status
Simulation time	1352392199 ps
CPU time	2.01 seconds
Started	Dec 20 12:32:47 PM PST 23
Finished	Dec 20 12:33:35 PM PST 23
Peak memory	215628 kb
Host	smart-0143e3e5-15df-4bad-98e7-49d68d332332
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117220582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp i_device_same_csr_outstanding.117220582
Directory	/workspace/1.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3645651769
Short name	T49
Test name
Test status
Simulation time	347751695 ps
CPU time	7.53 seconds
Started	Dec 20 12:32:32 PM PST 23
Finished	Dec 20 12:33:23 PM PST 23
Peak memory	215740 kb
Host	smart-467002a0-61c5-4fdb-a6c1-9196e0c56a4e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645651769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device _tl_intg_err.3645651769
Directory	/workspace/1.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2759351838
Short name	T89
Test name
Test status
Simulation time	49525792 ps
CPU time	2.13 seconds
Started	Dec 20 12:32:37 PM PST 23
Finished	Dec 20 12:33:22 PM PST 23
Peak memory	218496 kb
Host	smart-51d0d711-16e2-4046-a268-41b2f9ad9e73
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759351838 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2759351838
Directory	/workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3750097645
Short name	T167
Test name
Test status
Simulation time	31569719 ps
CPU time	1.84 seconds
Started	Dec 20 12:32:27 PM PST 23
Finished	Dec 20 12:33:12 PM PST 23
Peak memory	207600 kb
Host	smart-e1d8738a-66cb-42bb-9b04-81eac8d4de15
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750097645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw. 3750097645
Directory	/workspace/10.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.4293403259
Short name	T98
Test name
Test status
Simulation time	15511283 ps
CPU time	0.69 seconds
Started	Dec 20 12:32:28 PM PST 23
Finished	Dec 20 12:33:11 PM PST 23
Peak memory	204880 kb
Host	smart-54852d31-e2d0-42c7-aa9c-7de096abfa47
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293403259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test. 4293403259
Directory	/workspace/10.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.929650445
Short name	T174
Test name
Test status
Simulation time	258829326 ps
CPU time	1.83 seconds
Started	Dec 20 12:32:57 PM PST 23
Finished	Dec 20 12:33:48 PM PST 23
Peak memory	215636 kb
Host	smart-6e5faacb-d6de-47ac-bb3d-611f9463668f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929650445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s pi_device_same_csr_outstanding.929650445
Directory	/workspace/10.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3128221775
Short name	T20
Test name
Test status
Simulation time	121400949 ps
CPU time	2.14 seconds
Started	Dec 20 12:32:37 PM PST 23
Finished	Dec 20 12:33:23 PM PST 23
Peak memory	216048 kb
Host	smart-cbb01294-1402-49ec-b296-d425f96e6fc3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128221775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors. 3128221775
Directory	/workspace/10.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2812815214
Short name	T85
Test name
Test status
Simulation time	40831850 ps
CPU time	1.68 seconds
Started	Dec 20 12:32:25 PM PST 23
Finished	Dec 20 12:33:09 PM PST 23
Peak memory	217984 kb
Host	smart-52520e86-a0f5-49bc-b84a-0ca146995bf6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812815214 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2812815214
Directory	/workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1563229798
Short name	T134
Test name
Test status
Simulation time	51224362 ps
CPU time	1.48 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:16 PM PST 23
Peak memory	215896 kb
Host	smart-7fd9b68f-acc6-4227-b705-c5fa379dfed0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563229798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw. 1563229798
Directory	/workspace/11.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.2116852676
Short name	T103
Test name
Test status
Simulation time	12381266 ps
CPU time	0.71 seconds
Started	Dec 20 12:32:24 PM PST 23
Finished	Dec 20 12:33:06 PM PST 23
Peak memory	204980 kb
Host	smart-28e544f0-160a-4126-8896-01c6acb82e18
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116852676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test. 2116852676
Directory	/workspace/11.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3557193384
Short name	T173
Test name
Test status
Simulation time	45937070 ps
CPU time	2.73 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:17 PM PST 23
Peak memory	215760 kb
Host	smart-a350926f-8b05-497f-8a32-66acdfb64d6d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557193384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. spi_device_same_csr_outstanding.3557193384
Directory	/workspace/11.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3927819098
Short name	T156
Test name
Test status
Simulation time	53042465 ps
CPU time	3.8 seconds
Started	Dec 20 12:32:28 PM PST 23
Finished	Dec 20 12:33:14 PM PST 23
Peak memory	216000 kb
Host	smart-ac3be25b-63d0-47f9-9563-f1c39da19a64
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927819098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors. 3927819098
Directory	/workspace/11.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1494851209
Short name	T12
Test name
Test status
Simulation time	517936190 ps
CPU time	8.13 seconds
Started	Dec 20 12:32:33 PM PST 23
Finished	Dec 20 12:33:25 PM PST 23
Peak memory	215936 kb
Host	smart-9de7367f-9507-4975-bf96-af52b1a3c48d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494851209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic e_tl_intg_err.1494851209
Directory	/workspace/11.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2488248333
Short name	T121
Test name
Test status
Simulation time	65136938 ps
CPU time	1.85 seconds
Started	Dec 20 12:32:35 PM PST 23
Finished	Dec 20 12:33:20 PM PST 23
Peak memory	218244 kb
Host	smart-672097ce-4200-43c5-9bc3-9e47f0a0a914
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488248333 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2488248333
Directory	/workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2336111310
Short name	T148
Test name
Test status
Simulation time	150804314 ps
CPU time	0.69 seconds
Started	Dec 20 12:32:35 PM PST 23
Finished	Dec 20 12:33:19 PM PST 23
Peak memory	204984 kb
Host	smart-744ec765-c397-4ea0-b8b2-aa1372d439e7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336111310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test. 2336111310
Directory	/workspace/12.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2287526712
Short name	T105
Test name
Test status
Simulation time	53452765 ps
CPU time	1.69 seconds
Started	Dec 20 12:32:30 PM PST 23
Finished	Dec 20 12:33:14 PM PST 23
Peak memory	215768 kb
Host	smart-891c3580-b628-4961-9b9e-9bfeb24e372f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287526712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. spi_device_same_csr_outstanding.2287526712
Directory	/workspace/12.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2269905269
Short name	T93
Test name
Test status
Simulation time	595546397 ps
CPU time	3.08 seconds
Started	Dec 20 12:32:41 PM PST 23
Finished	Dec 20 12:33:28 PM PST 23
Peak memory	216300 kb
Host	smart-6b932129-dadb-4856-a50d-e5c0add81a42
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269905269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors. 2269905269
Directory	/workspace/12.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4255610999
Short name	T67
Test name
Test status
Simulation time	821691383 ps
CPU time	12.33 seconds
Started	Dec 20 12:33:01 PM PST 23
Finished	Dec 20 12:34:03 PM PST 23
Peak memory	215712 kb
Host	smart-f3458121-aa33-44f2-acb5-5271fb242bb5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255610999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic e_tl_intg_err.4255610999
Directory	/workspace/12.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3951223954
Short name	T91
Test name
Test status
Simulation time	37329269 ps
CPU time	1.88 seconds
Started	Dec 20 12:32:37 PM PST 23
Finished	Dec 20 12:33:21 PM PST 23
Peak memory	217840 kb
Host	smart-4a449a51-76a9-433f-b8c9-a96a8d4ee4d0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951223954 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3951223954
Directory	/workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1875030367
Short name	T34
Test name
Test status
Simulation time	164141256 ps
CPU time	2.18 seconds
Started	Dec 20 12:32:51 PM PST 23
Finished	Dec 20 12:33:40 PM PST 23
Peak memory	215600 kb
Host	smart-3d948be4-b079-4ae8-abd5-1c7eb7eb32ba
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875030367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw. 1875030367
Directory	/workspace/13.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.2625552527
Short name	T130
Test name
Test status
Simulation time	55496460 ps
CPU time	0.73 seconds
Started	Dec 20 12:32:40 PM PST 23
Finished	Dec 20 12:33:23 PM PST 23
Peak memory	204944 kb
Host	smart-fb54d874-86d4-4fb5-9533-9d1995b1ca75
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625552527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test. 2625552527
Directory	/workspace/13.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3357243323
Short name	T172
Test name
Test status
Simulation time	283270361 ps
CPU time	1.73 seconds
Started	Dec 20 12:32:25 PM PST 23
Finished	Dec 20 12:33:10 PM PST 23
Peak memory	215572 kb
Host	smart-15bba6d2-67d2-48f2-b6cf-b23c6100c5a7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357243323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. spi_device_same_csr_outstanding.3357243323
Directory	/workspace/13.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3823093994
Short name	T112
Test name
Test status
Simulation time	43661986 ps
CPU time	1.54 seconds
Started	Dec 20 12:32:30 PM PST 23
Finished	Dec 20 12:33:14 PM PST 23
Peak memory	215996 kb
Host	smart-ff418213-092d-4439-b618-875779cf9544
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823093994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors. 3823093994
Directory	/workspace/13.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.641221072
Short name	T66
Test name
Test status
Simulation time	1103752759 ps
CPU time	17.07 seconds
Started	Dec 20 12:32:46 PM PST 23
Finished	Dec 20 12:33:48 PM PST 23
Peak memory	215776 kb
Host	smart-d7a42257-893c-490e-ab4e-0612669c3152
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641221072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device _tl_intg_err.641221072
Directory	/workspace/13.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2515785516
Short name	T92
Test name
Test status
Simulation time	40954233 ps
CPU time	2.23 seconds
Started	Dec 20 12:32:38 PM PST 23
Finished	Dec 20 12:33:24 PM PST 23
Peak memory	218088 kb
Host	smart-db704c55-271e-41b2-98d0-d0a795f5395c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515785516 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2515785516
Directory	/workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2964060234
Short name	T33
Test name
Test status
Simulation time	102664468 ps
CPU time	2.39 seconds
Started	Dec 20 12:34:11 PM PST 23
Finished	Dec 20 12:34:20 PM PST 23
Peak memory	215280 kb
Host	smart-1e144022-f25a-420c-b51c-ca729332bb15
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964060234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw. 2964060234
Directory	/workspace/14.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.693341108
Short name	T59
Test name
Test status
Simulation time	565553578 ps
CPU time	3.03 seconds
Started	Dec 20 12:33:55 PM PST 23
Finished	Dec 20 12:34:18 PM PST 23
Peak memory	214664 kb
Host	smart-d8c6bdcc-1e62-4edc-9774-bb4b55b3fdff
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693341108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s pi_device_same_csr_outstanding.693341108
Directory	/workspace/14.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2994168485
Short name	T138
Test name
Test status
Simulation time	129730169 ps
CPU time	3.12 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:17 PM PST 23
Peak memory	215920 kb
Host	smart-d1c20414-7a06-429f-9410-7cb9fb1f8c56
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994168485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors. 2994168485
Directory	/workspace/14.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1612775713
Short name	T64
Test name
Test status
Simulation time	210643676 ps
CPU time	12.41 seconds
Started	Dec 20 12:32:52 PM PST 23
Finished	Dec 20 12:33:52 PM PST 23
Peak memory	215800 kb
Host	smart-7145b6f7-1615-4e3a-b2f1-381885eba719
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612775713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic e_tl_intg_err.1612775713
Directory	/workspace/14.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.488285865
Short name	T17
Test name
Test status
Simulation time	45267531 ps
CPU time	1.83 seconds
Started	Dec 20 12:34:10 PM PST 23
Finished	Dec 20 12:34:19 PM PST 23
Peak memory	216848 kb
Host	smart-6270a37e-9165-4db0-8a94-9d9dcfb743d2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488285865 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.488285865
Directory	/workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.356442356
Short name	T38
Test name
Test status
Simulation time	102922326 ps
CPU time	2.63 seconds
Started	Dec 20 12:34:11 PM PST 23
Finished	Dec 20 12:34:21 PM PST 23
Peak memory	215292 kb
Host	smart-fec6ff78-0dba-4e1f-960c-66fea10114f6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356442356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.356442356
Directory	/workspace/15.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.1267053403
Short name	T99
Test name
Test status
Simulation time	12915138 ps
CPU time	0.69 seconds
Started	Dec 20 12:32:39 PM PST 23
Finished	Dec 20 12:33:24 PM PST 23
Peak memory	204956 kb
Host	smart-71ba829b-c982-4cc0-ae86-25d84086e519
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267053403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test. 1267053403
Directory	/workspace/15.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1957536026
Short name	T29
Test name
Test status
Simulation time	49240095 ps
CPU time	2.93 seconds
Started	Dec 20 12:32:24 PM PST 23
Finished	Dec 20 12:33:09 PM PST 23
Peak memory	215880 kb
Host	smart-335ef238-cf97-4f02-939d-01d184380ce1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957536026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. spi_device_same_csr_outstanding.1957536026
Directory	/workspace/15.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3408882928
Short name	T101
Test name
Test status
Simulation time	199854034 ps
CPU time	5.19 seconds
Started	Dec 20 12:34:11 PM PST 23
Finished	Dec 20 12:34:23 PM PST 23
Peak memory	215604 kb
Host	smart-26fb02d5-0720-4aee-a67a-8090979b2c63
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408882928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors. 3408882928
Directory	/workspace/15.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.24425452
Short name	T110
Test name
Test status
Simulation time	693459145 ps
CPU time	15.23 seconds
Started	Dec 20 12:34:11 PM PST 23
Finished	Dec 20 12:34:33 PM PST 23
Peak memory	215460 kb
Host	smart-11e24856-e263-4ae0-a5b4-b55284f097d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24425452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_ tl_intg_err.24425452
Directory	/workspace/15.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.742251860
Short name	T144
Test name
Test status
Simulation time	51153983 ps
CPU time	1.48 seconds
Started	Dec 20 12:33:01 PM PST 23
Finished	Dec 20 12:33:52 PM PST 23
Peak memory	215884 kb
Host	smart-589a83e7-359d-47e4-92cd-cc8099145de3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742251860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.742251860
Directory	/workspace/16.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.2924128881
Short name	T87
Test name
Test status
Simulation time	12808513 ps
CPU time	0.72 seconds
Started	Dec 20 12:32:54 PM PST 23
Finished	Dec 20 12:33:42 PM PST 23
Peak memory	204768 kb
Host	smart-59705c9f-1819-4863-b758-3d00d2d22975
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924128881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test. 2924128881
Directory	/workspace/16.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.285491424
Short name	T62
Test name
Test status
Simulation time	830437128 ps
CPU time	12.07 seconds
Started	Dec 20 12:34:11 PM PST 23
Finished	Dec 20 12:34:30 PM PST 23
Peak memory	216680 kb
Host	smart-fe6aa9b8-a3cc-40a1-ac00-e65868e47ec4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285491424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device _tl_intg_err.285491424
Directory	/workspace/16.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4262009385
Short name	T129
Test name
Test status
Simulation time	112498909 ps
CPU time	2.26 seconds
Started	Dec 20 12:34:29 PM PST 23
Finished	Dec 20 12:34:32 PM PST 23
Peak memory	218200 kb
Host	smart-77bc62e1-a158-4db3-b407-9a3d49dc375c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262009385 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4262009385
Directory	/workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.590415047
Short name	T36
Test name
Test status
Simulation time	38583794 ps
CPU time	2.43 seconds
Started	Dec 20 12:32:37 PM PST 23
Finished	Dec 20 12:33:24 PM PST 23
Peak memory	215888 kb
Host	smart-b0c16be1-77c1-40b6-9e10-d2951ca3a275
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590415047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.590415047
Directory	/workspace/17.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.702324193
Short name	T171
Test name
Test status
Simulation time	46110169 ps
CPU time	0.8 seconds
Started	Dec 20 12:34:05 PM PST 23
Finished	Dec 20 12:34:17 PM PST 23
Peak memory	203600 kb
Host	smart-992295e8-a3b0-403f-9918-3614a57a836e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702324193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.702324193
Directory	/workspace/17.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3711348684
Short name	T100
Test name
Test status
Simulation time	64156001 ps
CPU time	3.72 seconds
Started	Dec 20 12:32:35 PM PST 23
Finished	Dec 20 12:33:22 PM PST 23
Peak memory	215896 kb
Host	smart-9a4b3c96-4b44-4ae3-b535-3b22a29277f4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711348684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. spi_device_same_csr_outstanding.3711348684
Directory	/workspace/17.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2103584183
Short name	T109
Test name
Test status
Simulation time	219989288 ps
CPU time	3.94 seconds
Started	Dec 20 12:32:37 PM PST 23
Finished	Dec 20 12:33:24 PM PST 23
Peak memory	216192 kb
Host	smart-89c3990d-95d3-409b-ad48-3d8b4cc9e9a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103584183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors. 2103584183
Directory	/workspace/17.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.59376827
Short name	T168
Test name
Test status
Simulation time	27666064 ps
CPU time	2.01 seconds
Started	Dec 20 12:32:54 PM PST 23
Finished	Dec 20 12:33:43 PM PST 23
Peak memory	218248 kb
Host	smart-a450ff80-16c0-4176-86a3-0f618e16272f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59376827 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.59376827
Directory	/workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.713285389
Short name	T114
Test name
Test status
Simulation time	152913498 ps
CPU time	2.51 seconds
Started	Dec 20 12:32:52 PM PST 23
Finished	Dec 20 12:33:41 PM PST 23
Peak memory	215896 kb
Host	smart-95e85c4d-5020-4127-98b6-eca76d818391
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713285389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.713285389
Directory	/workspace/18.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.3722251930
Short name	T71
Test name
Test status
Simulation time	12292919 ps
CPU time	0.69 seconds
Started	Dec 20 12:32:52 PM PST 23
Finished	Dec 20 12:33:40 PM PST 23
Peak memory	204952 kb
Host	smart-672b302c-3e09-4aba-8b03-201b3c55dedf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722251930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test. 3722251930
Directory	/workspace/18.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1944400437
Short name	T50
Test name
Test status
Simulation time	346435106 ps
CPU time	3.48 seconds
Started	Dec 20 12:33:06 PM PST 23
Finished	Dec 20 12:33:59 PM PST 23
Peak memory	215848 kb
Host	smart-33eda7a8-a4ea-4964-b255-25b62f654441
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944400437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. spi_device_same_csr_outstanding.1944400437
Directory	/workspace/18.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1833327659
Short name	T47
Test name
Test status
Simulation time	49174259 ps
CPU time	3.23 seconds
Started	Dec 20 12:34:01 PM PST 23
Finished	Dec 20 12:34:19 PM PST 23
Peak memory	214804 kb
Host	smart-84650748-b174-415b-b41f-ad9ad24cc752
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833327659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors. 1833327659
Directory	/workspace/18.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.768159880
Short name	T27
Test name
Test status
Simulation time	163921183 ps
CPU time	6.13 seconds
Started	Dec 20 12:32:52 PM PST 23
Finished	Dec 20 12:33:46 PM PST 23
Peak memory	215844 kb
Host	smart-d7626e20-d735-4c55-86d9-14f374e2efce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768159880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device _tl_intg_err.768159880
Directory	/workspace/18.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1952449263
Short name	T84
Test name
Test status
Simulation time	43605490 ps
CPU time	1.78 seconds
Started	Dec 20 12:32:50 PM PST 23
Finished	Dec 20 12:33:38 PM PST 23
Peak memory	217368 kb
Host	smart-59fab6e8-4043-4a41-8e79-f7754f0eb1d1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952449263 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1952449263
Directory	/workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1960723259
Short name	T131
Test name
Test status
Simulation time	82904801 ps
CPU time	1.28 seconds
Started	Dec 20 12:33:04 PM PST 23
Finished	Dec 20 12:33:55 PM PST 23
Peak memory	207744 kb
Host	smart-2fd3a064-cdf7-48dc-b92f-8fbb3bbc94d6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960723259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw. 1960723259
Directory	/workspace/19.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2093648577
Short name	T52
Test name
Test status
Simulation time	84788374 ps
CPU time	1.98 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:16 PM PST 23
Peak memory	215768 kb
Host	smart-62e1feea-7493-4173-8d9b-6ba8976d0490
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093648577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. spi_device_same_csr_outstanding.2093648577
Directory	/workspace/19.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1864876962
Short name	T24
Test name
Test status
Simulation time	315317531 ps
CPU time	2.46 seconds
Started	Dec 20 12:33:04 PM PST 23
Finished	Dec 20 12:33:56 PM PST 23
Peak memory	216208 kb
Host	smart-192bd3a8-d4d1-4003-97f0-cb6e7d054acb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864876962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors. 1864876962
Directory	/workspace/19.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3575480171
Short name	T125
Test name
Test status
Simulation time	294037648 ps
CPU time	7.75 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:23 PM PST 23
Peak memory	215908 kb
Host	smart-decd43d9-9cf1-4394-afb4-0116ed15b369
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575480171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic e_tl_intg_err.3575480171
Directory	/workspace/19.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3019333299
Short name	T132
Test name
Test status
Simulation time	2122294882 ps
CPU time	9.14 seconds
Started	Dec 20 12:32:35 PM PST 23
Finished	Dec 20 12:33:27 PM PST 23
Peak memory	216764 kb
Host	smart-a329a678-66db-4474-aae4-ca510dbff330
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019333299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_aliasing.3019333299
Directory	/workspace/2.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3444801111
Short name	T161
Test name
Test status
Simulation time	434549086 ps
CPU time	23.82 seconds
Started	Dec 20 12:32:38 PM PST 23
Finished	Dec 20 12:33:46 PM PST 23
Peak memory	207660 kb
Host	smart-fed0e694-5d46-4758-84d3-30156851c4ea
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444801111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_bit_bash.3444801111
Directory	/workspace/2.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1757133938
Short name	T160
Test name
Test status
Simulation time	107933193 ps
CPU time	1.2 seconds
Started	Dec 20 12:32:35 PM PST 23
Finished	Dec 20 12:33:20 PM PST 23
Peak memory	207616 kb
Host	smart-b4862687-7d9e-4604-991d-7f6c33e1389f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757133938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_hw_reset.1757133938
Directory	/workspace/2.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3024858519
Short name	T54
Test name
Test status
Simulation time	38393635 ps
CPU time	1.12 seconds
Started	Dec 20 12:32:37 PM PST 23
Finished	Dec 20 12:33:22 PM PST 23
Peak memory	216928 kb
Host	smart-65472766-bf61-40a8-a977-e48bc18cd914
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024858519 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3024858519
Directory	/workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1901611623
Short name	T37
Test name
Test status
Simulation time	138030358 ps
CPU time	1.78 seconds
Started	Dec 20 12:32:26 PM PST 23
Finished	Dec 20 12:33:11 PM PST 23
Peak memory	215968 kb
Host	smart-49a3969f-a916-46ba-ba7c-fd7103c5192f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901611623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1 901611623
Directory	/workspace/2.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.2432079131
Short name	T149
Test name
Test status
Simulation time	15514254 ps
CPU time	0.71 seconds
Started	Dec 20 12:32:38 PM PST 23
Finished	Dec 20 12:33:22 PM PST 23
Peak memory	204984 kb
Host	smart-25d71984-9c98-4135-ab6d-c8a32635c652
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432079131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2 432079131
Directory	/workspace/2.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3143915526
Short name	T141
Test name
Test status
Simulation time	36017017 ps
CPU time	2.53 seconds
Started	Dec 20 12:32:39 PM PST 23
Finished	Dec 20 12:33:26 PM PST 23
Peak memory	215844 kb
Host	smart-b99149a5-9ee9-4b7b-88f1-39ea7babf0ae
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143915526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi _device_mem_partial_access.3143915526
Directory	/workspace/2.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2034569713
Short name	T16
Test name
Test status
Simulation time	935986335 ps
CPU time	5.32 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:19 PM PST 23
Peak memory	215856 kb
Host	smart-1eb80b1d-2b9b-4b4c-b846-ed0478368661
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034569713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me m_walk.2034569713
Directory	/workspace/2.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3726674067
Short name	T82
Test name
Test status
Simulation time	300351193 ps
CPU time	1.93 seconds
Started	Dec 20 12:34:11 PM PST 23
Finished	Dec 20 12:34:20 PM PST 23
Peak memory	215256 kb
Host	smart-2441fb3b-f398-418a-8002-c2347416ef7c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726674067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s pi_device_same_csr_outstanding.3726674067
Directory	/workspace/2.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3719850930
Short name	T21
Test name
Test status
Simulation time	29741385 ps
CPU time	1.82 seconds
Started	Dec 20 12:33:55 PM PST 23
Finished	Dec 20 12:34:17 PM PST 23
Peak memory	214668 kb
Host	smart-b0480ee5-8695-4002-9c5a-75f569ce52f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719850930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3 719850930
Directory	/workspace/2.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4185841436
Short name	T11
Test name
Test status
Simulation time	236392582 ps
CPU time	6.44 seconds
Started	Dec 20 12:32:39 PM PST 23
Finished	Dec 20 12:33:29 PM PST 23
Peak memory	215664 kb
Host	smart-f1d48f33-d579-4631-8e17-123c124650a5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185841436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device _tl_intg_err.4185841436
Directory	/workspace/2.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.3221215044
Short name	T94
Test name
Test status
Simulation time	20903486 ps
CPU time	0.68 seconds
Started	Dec 20 12:32:35 PM PST 23
Finished	Dec 20 12:33:18 PM PST 23
Peak memory	204976 kb
Host	smart-a17e5343-8cca-4890-a67d-af74766a283c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221215044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test. 3221215044
Directory	/workspace/20.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.4281658416
Short name	T113
Test name
Test status
Simulation time	31688929 ps
CPU time	0.72 seconds
Started	Dec 20 12:32:27 PM PST 23
Finished	Dec 20 12:33:10 PM PST 23
Peak memory	204880 kb
Host	smart-f63ae95a-402d-4203-89f1-9f0e5fcf5107
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281658416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test. 4281658416
Directory	/workspace/21.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.3719742990
Short name	T55
Test name
Test status
Simulation time	34953238 ps
CPU time	0.69 seconds
Started	Dec 20 12:32:25 PM PST 23
Finished	Dec 20 12:33:09 PM PST 23
Peak memory	204992 kb
Host	smart-53415c0c-c9eb-4b35-aab3-cc6f49ca477c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719742990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test. 3719742990
Directory	/workspace/22.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.1084592449
Short name	T69
Test name
Test status
Simulation time	39183807 ps
CPU time	0.69 seconds
Started	Dec 20 12:32:27 PM PST 23
Finished	Dec 20 12:33:11 PM PST 23
Peak memory	205020 kb
Host	smart-915489f7-22c2-4f20-ba52-0482daa376f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084592449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test. 1084592449
Directory	/workspace/23.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3142597286
Short name	T74
Test name
Test status
Simulation time	49222480 ps
CPU time	0.73 seconds
Started	Dec 20 12:32:29 PM PST 23
Finished	Dec 20 12:33:13 PM PST 23
Peak memory	204952 kb
Host	smart-de26256e-99ae-4439-8e44-3054d4ca69db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142597286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test. 3142597286
Directory	/workspace/24.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.658026897
Short name	T88
Test name
Test status
Simulation time	14809167 ps
CPU time	0.71 seconds
Started	Dec 20 12:32:30 PM PST 23
Finished	Dec 20 12:33:13 PM PST 23
Peak memory	204940 kb
Host	smart-4ed72704-745a-4624-bc0c-4559acb708f5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658026897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.658026897
Directory	/workspace/25.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.2007479521
Short name	T14
Test name
Test status
Simulation time	82489113 ps
CPU time	0.7 seconds
Started	Dec 20 12:32:36 PM PST 23
Finished	Dec 20 12:33:21 PM PST 23
Peak memory	204960 kb
Host	smart-616e75a5-01e8-429f-8fae-a34860c70672
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007479521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test. 2007479521
Directory	/workspace/26.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.1726220206
Short name	T7
Test name
Test status
Simulation time	24304590 ps
CPU time	0.67 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:16 PM PST 23
Peak memory	204828 kb
Host	smart-694eaaf8-c80e-4c8d-b393-d515310bee6f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726220206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test. 1726220206
Directory	/workspace/27.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.4273468858
Short name	T107
Test name
Test status
Simulation time	13746354 ps
CPU time	0.69 seconds
Started	Dec 20 12:32:30 PM PST 23
Finished	Dec 20 12:33:13 PM PST 23
Peak memory	204912 kb
Host	smart-6852bb15-115f-4524-9642-bdffd5e55a88
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273468858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test. 4273468858
Directory	/workspace/28.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.3969925127
Short name	T58
Test name
Test status
Simulation time	53384497 ps
CPU time	0.68 seconds
Started	Dec 20 12:32:26 PM PST 23
Finished	Dec 20 12:33:09 PM PST 23
Peak memory	204820 kb
Host	smart-09809bb8-fef7-4c2e-a150-72ba97dc66ad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969925127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test. 3969925127
Directory	/workspace/29.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4011612886
Short name	T163
Test name
Test status
Simulation time	1475342908 ps
CPU time	9.63 seconds
Started	Dec 20 12:32:28 PM PST 23
Finished	Dec 20 12:33:20 PM PST 23
Peak memory	217040 kb
Host	smart-3bef2e4c-4dc3-4c92-9155-8c8c8c787199
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011612886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_aliasing.4011612886
Directory	/workspace/3.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2341322998
Short name	T97
Test name
Test status
Simulation time	2775046136 ps
CPU time	23.8 seconds
Started	Dec 20 12:32:38 PM PST 23
Finished	Dec 20 12:33:46 PM PST 23
Peak memory	207668 kb
Host	smart-183f2047-5a9d-4c57-aa9e-b399ddba3cd3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341322998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_bit_bash.2341322998
Directory	/workspace/3.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3025416982
Short name	T151
Test name
Test status
Simulation time	24616763 ps
CPU time	1.36 seconds
Started	Dec 20 12:34:16 PM PST 23
Finished	Dec 20 12:34:21 PM PST 23
Peak memory	215328 kb
Host	smart-1bb5d045-5639-48a5-b4ea-82c0fa052cb6
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025416982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_hw_reset.3025416982
Directory	/workspace/3.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4200538405
Short name	T170
Test name
Test status
Simulation time	16501051 ps
CPU time	1.44 seconds
Started	Dec 20 12:33:06 PM PST 23
Finished	Dec 20 12:33:57 PM PST 23
Peak memory	217508 kb
Host	smart-f1b6f066-e015-406b-a317-f1d7ef64d669
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200538405 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4200538405
Directory	/workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.276170767
Short name	T135
Test name
Test status
Simulation time	149552640 ps
CPU time	1.64 seconds
Started	Dec 20 12:34:16 PM PST 23
Finished	Dec 20 12:34:22 PM PST 23
Peak memory	207224 kb
Host	smart-a4bf38d1-86f8-4e60-96f1-c6abb49fcc36
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276170767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.276170767
Directory	/workspace/3.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.4158127211
Short name	T79
Test name
Test status
Simulation time	30217004 ps
CPU time	0.67 seconds
Started	Dec 20 12:34:28 PM PST 23
Finished	Dec 20 12:34:29 PM PST 23
Peak memory	204680 kb
Host	smart-1b63b35e-7299-4280-8811-9add636255e0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158127211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4 158127211
Directory	/workspace/3.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3185057589
Short name	T41
Test name
Test status
Simulation time	279012666 ps
CPU time	2.7 seconds
Started	Dec 20 12:32:39 PM PST 23
Finished	Dec 20 12:33:25 PM PST 23
Peak memory	215844 kb
Host	smart-b8c843df-c99d-4e7b-a5ff-81732caa8277
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185057589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi _device_mem_partial_access.3185057589
Directory	/workspace/3.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4174154732
Short name	T90
Test name
Test status
Simulation time	139110696 ps
CPU time	7.96 seconds
Started	Dec 20 12:32:29 PM PST 23
Finished	Dec 20 12:33:20 PM PST 23
Peak memory	215844 kb
Host	smart-eb7000e3-4625-47c6-901c-4c18d56ce664
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174154732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me m_walk.4174154732
Directory	/workspace/3.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.748954535
Short name	T111
Test name
Test status
Simulation time	68576688 ps
CPU time	3.84 seconds
Started	Dec 20 12:32:39 PM PST 23
Finished	Dec 20 12:33:27 PM PST 23
Peak memory	215792 kb
Host	smart-c9129997-5633-4b14-80c8-88c79fc4d4ca
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748954535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp i_device_same_csr_outstanding.748954535
Directory	/workspace/3.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2176689151
Short name	T9
Test name
Test status
Simulation time	174662119 ps
CPU time	4.34 seconds
Started	Dec 20 12:34:28 PM PST 23
Finished	Dec 20 12:34:33 PM PST 23
Peak memory	215828 kb
Host	smart-1e222e9c-58a1-40e0-b49b-6d5605894e05
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176689151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2 176689151
Directory	/workspace/3.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3402331828
Short name	T22
Test name
Test status
Simulation time	931278931 ps
CPU time	22.27 seconds
Started	Dec 20 12:32:23 PM PST 23
Finished	Dec 20 12:33:28 PM PST 23
Peak memory	215800 kb
Host	smart-d1267d93-ac43-414f-a25a-d0029c7be869
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402331828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device _tl_intg_err.3402331828
Directory	/workspace/3.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.3393319395
Short name	T75
Test name
Test status
Simulation time	60524269 ps
CPU time	0.71 seconds
Started	Dec 20 12:34:34 PM PST 23
Finished	Dec 20 12:34:43 PM PST 23
Peak memory	204700 kb
Host	smart-b41540b6-dc76-48dd-925c-797e0dc3db0f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393319395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test. 3393319395
Directory	/workspace/30.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.1538898799
Short name	T8
Test name
Test status
Simulation time	54662464 ps
CPU time	0.76 seconds
Started	Dec 20 12:34:34 PM PST 23
Finished	Dec 20 12:34:43 PM PST 23
Peak memory	204692 kb
Host	smart-b29983e1-0829-47db-b7de-e65172ea309e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538898799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test. 1538898799
Directory	/workspace/31.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.565219821
Short name	T150
Test name
Test status
Simulation time	46486259 ps
CPU time	0.76 seconds
Started	Dec 20 12:32:39 PM PST 23
Finished	Dec 20 12:33:23 PM PST 23
Peak memory	205068 kb
Host	smart-1a59d77f-cf74-41a9-81f0-0d5e5bf1d76a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565219821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.565219821
Directory	/workspace/32.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.1698987620
Short name	T152
Test name
Test status
Simulation time	42350431 ps
CPU time	0.69 seconds
Started	Dec 20 12:32:54 PM PST 23
Finished	Dec 20 12:33:43 PM PST 23
Peak memory	204788 kb
Host	smart-17bf00ef-d6eb-429e-bc10-5bf549523522
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698987620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test. 1698987620
Directory	/workspace/33.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.3818532506
Short name	T77
Test name
Test status
Simulation time	39697795 ps
CPU time	0.74 seconds
Started	Dec 20 12:34:34 PM PST 23
Finished	Dec 20 12:34:43 PM PST 23
Peak memory	204716 kb
Host	smart-ee11f622-78f3-4078-9983-b7f399d0611c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818532506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test. 3818532506
Directory	/workspace/34.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.4117052716
Short name	T146
Test name
Test status
Simulation time	48209348 ps
CPU time	0.77 seconds
Started	Dec 20 12:34:35 PM PST 23
Finished	Dec 20 12:34:43 PM PST 23
Peak memory	204696 kb
Host	smart-a8b1a944-20b5-4f1e-bb15-0a5109e2697e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117052716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test. 4117052716
Directory	/workspace/35.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.202775452
Short name	T44
Test name
Test status
Simulation time	15377299 ps
CPU time	0.7 seconds
Started	Dec 20 12:34:12 PM PST 23
Finished	Dec 20 12:34:19 PM PST 23
Peak memory	203608 kb
Host	smart-82b1c2fd-9899-4339-b03a-f4b4ff1d29d8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202775452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.202775452
Directory	/workspace/36.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.4216199776
Short name	T142
Test name
Test status
Simulation time	11356137 ps
CPU time	0.7 seconds
Started	Dec 20 12:32:30 PM PST 23
Finished	Dec 20 12:33:13 PM PST 23
Peak memory	204948 kb
Host	smart-426436bc-b516-4578-aa8d-9830adec8e86
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216199776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test. 4216199776
Directory	/workspace/37.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.1161903557
Short name	T70
Test name
Test status
Simulation time	57885906 ps
CPU time	0.73 seconds
Started	Dec 20 12:32:25 PM PST 23
Finished	Dec 20 12:33:08 PM PST 23
Peak memory	204956 kb
Host	smart-30022617-86b5-411b-9363-3a4982fe99f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161903557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test. 1161903557
Directory	/workspace/38.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.2459940880
Short name	T122
Test name
Test status
Simulation time	35420670 ps
CPU time	0.66 seconds
Started	Dec 20 12:32:45 PM PST 23
Finished	Dec 20 12:33:30 PM PST 23
Peak memory	204788 kb
Host	smart-2916d98e-9ce8-4fa5-9087-91ca861f4b7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459940880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test. 2459940880
Directory	/workspace/39.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3035406609
Short name	T80
Test name
Test status
Simulation time	1160079811 ps
CPU time	17.25 seconds
Started	Dec 20 12:32:23 PM PST 23
Finished	Dec 20 12:33:21 PM PST 23
Peak memory	207664 kb
Host	smart-5fe0636f-ef39-4ad4-96d1-1a3009a3b36a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035406609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_aliasing.3035406609
Directory	/workspace/4.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.428272440
Short name	T119
Test name
Test status
Simulation time	8330184428 ps
CPU time	40.09 seconds
Started	Dec 20 12:32:25 PM PST 23
Finished	Dec 20 12:33:48 PM PST 23
Peak memory	207984 kb
Host	smart-7ae13452-1c63-461d-be04-11605ec3f13e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428272440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr _bit_bash.428272440
Directory	/workspace/4.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2008191097
Short name	T30
Test name
Test status
Simulation time	60049919 ps
CPU time	1.16 seconds
Started	Dec 20 12:32:56 PM PST 23
Finished	Dec 20 12:33:46 PM PST 23
Peak memory	207728 kb
Host	smart-fb6f6de8-5ea7-4b89-8201-d0c3bce10167
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008191097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_hw_reset.2008191097
Directory	/workspace/4.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4064111365
Short name	T5
Test name
Test status
Simulation time	21914926 ps
CPU time	1.52 seconds
Started	Dec 20 12:32:26 PM PST 23
Finished	Dec 20 12:33:09 PM PST 23
Peak memory	217164 kb
Host	smart-96837d8c-b71c-41f1-90ed-f51c5c8031a1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064111365 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4064111365
Directory	/workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.978237449
Short name	T116
Test name
Test status
Simulation time	37620892 ps
CPU time	2.31 seconds
Started	Dec 20 12:32:26 PM PST 23
Finished	Dec 20 12:33:12 PM PST 23
Peak memory	215872 kb
Host	smart-1fcc4884-d61a-45ff-a439-316e49a02871
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978237449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.978237449
Directory	/workspace/4.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.1565761734
Short name	T57
Test name
Test status
Simulation time	49293969 ps
CPU time	0.7 seconds
Started	Dec 20 12:32:29 PM PST 23
Finished	Dec 20 12:33:12 PM PST 23
Peak memory	205004 kb
Host	smart-0eb84298-b3ff-436e-a028-da1ce2618b78
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565761734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1 565761734
Directory	/workspace/4.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1236112426
Short name	T15
Test name
Test status
Simulation time	77964305 ps
CPU time	2.54 seconds
Started	Dec 20 12:32:28 PM PST 23
Finished	Dec 20 12:33:13 PM PST 23
Peak memory	215880 kb
Host	smart-e71dfbbb-8df1-4a1c-aadb-3a5e86dcee9a
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236112426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi _device_mem_partial_access.1236112426
Directory	/workspace/4.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1510010052
Short name	T120
Test name
Test status
Simulation time	456342155 ps
CPU time	5.24 seconds
Started	Dec 20 12:32:27 PM PST 23
Finished	Dec 20 12:33:16 PM PST 23
Peak memory	215900 kb
Host	smart-ff3dc5bd-fd65-4aee-8ac6-f4a664bf9cee
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510010052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me m_walk.1510010052
Directory	/workspace/4.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.931065091
Short name	T153
Test name
Test status
Simulation time	75405298 ps
CPU time	1.74 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:16 PM PST 23
Peak memory	215872 kb
Host	smart-bbaca67a-cf7e-4935-9dee-2e22fb2a5c64
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931065091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp i_device_same_csr_outstanding.931065091
Directory	/workspace/4.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2144698676
Short name	T45
Test name
Test status
Simulation time	191574782 ps
CPU time	2.43 seconds
Started	Dec 20 12:32:36 PM PST 23
Finished	Dec 20 12:33:22 PM PST 23
Peak memory	216120 kb
Host	smart-512a9c1d-151c-49e5-87e8-fe10a0cdca2a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144698676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2 144698676
Directory	/workspace/4.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2912590053
Short name	T65
Test name
Test status
Simulation time	602349283 ps
CPU time	7.8 seconds
Started	Dec 20 12:32:21 PM PST 23
Finished	Dec 20 12:33:10 PM PST 23
Peak memory	216084 kb
Host	smart-f29f7fa7-3607-49d0-b186-b943be6de247
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912590053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device _tl_intg_err.2912590053
Directory	/workspace/4.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.1363463403
Short name	T72
Test name
Test status
Simulation time	18642543 ps
CPU time	0.73 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:15 PM PST 23
Peak memory	204980 kb
Host	smart-e3da1697-d5a4-4390-8f32-ac7e51886002
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363463403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test. 1363463403
Directory	/workspace/41.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.4223599537
Short name	T13
Test name
Test status
Simulation time	16286226 ps
CPU time	0.69 seconds
Started	Dec 20 12:33:06 PM PST 23
Finished	Dec 20 12:33:56 PM PST 23
Peak memory	205008 kb
Host	smart-f715c403-f596-4778-ade7-b27e643fe0e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223599537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test. 4223599537
Directory	/workspace/42.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.3419869278
Short name	T139
Test name
Test status
Simulation time	19724390 ps
CPU time	0.75 seconds
Started	Dec 20 12:34:11 PM PST 23
Finished	Dec 20 12:34:19 PM PST 23
Peak memory	204284 kb
Host	smart-f5991d28-e333-4e39-971d-bab7a7e74104
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419869278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test. 3419869278
Directory	/workspace/43.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.3887139203
Short name	T147
Test name
Test status
Simulation time	51929406 ps
CPU time	0.74 seconds
Started	Dec 20 12:32:46 PM PST 23
Finished	Dec 20 12:33:31 PM PST 23
Peak memory	204940 kb
Host	smart-e2aaedf1-0224-4efe-ab0d-1266845ca706
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887139203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test. 3887139203
Directory	/workspace/44.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.2584930034
Short name	T175
Test name
Test status
Simulation time	40728066 ps
CPU time	0.77 seconds
Started	Dec 20 12:34:11 PM PST 23
Finished	Dec 20 12:34:19 PM PST 23
Peak memory	204312 kb
Host	smart-2ee0c63e-dc9e-408d-adb1-0878d1feb5d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584930034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test. 2584930034
Directory	/workspace/45.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.1114444936
Short name	T126
Test name
Test status
Simulation time	35593843 ps
CPU time	0.71 seconds
Started	Dec 20 12:32:45 PM PST 23
Finished	Dec 20 12:33:30 PM PST 23
Peak memory	204892 kb
Host	smart-a7c7a4b8-093a-4e54-b1ed-92c88499b1b0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114444936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test. 1114444936
Directory	/workspace/46.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3263538421
Short name	T133
Test name
Test status
Simulation time	13675996 ps
CPU time	0.72 seconds
Started	Dec 20 12:32:41 PM PST 23
Finished	Dec 20 12:33:25 PM PST 23
Peak memory	204948 kb
Host	smart-a0e4ba2a-afa9-4c79-be5a-b4dabbcfd8cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263538421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test. 3263538421
Directory	/workspace/47.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.3434586143
Short name	T61
Test name
Test status
Simulation time	13350332 ps
CPU time	0.71 seconds
Started	Dec 20 12:32:27 PM PST 23
Finished	Dec 20 12:33:10 PM PST 23
Peak memory	204808 kb
Host	smart-185c6965-3dfc-41e5-ab22-9a24814c9558
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434586143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test. 3434586143
Directory	/workspace/48.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.2252674987
Short name	T28
Test name
Test status
Simulation time	16611780 ps
CPU time	0.75 seconds
Started	Dec 20 12:32:42 PM PST 23
Finished	Dec 20 12:33:26 PM PST 23
Peak memory	204888 kb
Host	smart-c6ae26ca-9afa-4e7b-b558-c93832d25f75
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252674987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test. 2252674987
Directory	/workspace/49.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.552531965
Short name	T118
Test name
Test status
Simulation time	22245313 ps
CPU time	1.25 seconds
Started	Dec 20 12:34:35 PM PST 23
Finished	Dec 20 12:34:54 PM PST 23
Peak memory	216828 kb
Host	smart-e5da7c6c-f970-421c-a8c3-0e81b23d46db
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552531965 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.552531965
Directory	/workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3226033823
Short name	T154
Test name
Test status
Simulation time	41096295 ps
CPU time	1.89 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:16 PM PST 23
Peak memory	215800 kb
Host	smart-ebeb7ba8-d30c-4909-b5ab-007f9b9b9bd5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226033823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3 226033823
Directory	/workspace/5.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.1394191079
Short name	T124
Test name
Test status
Simulation time	38603281 ps
CPU time	0.68 seconds
Started	Dec 20 12:32:33 PM PST 23
Finished	Dec 20 12:33:17 PM PST 23
Peak memory	204792 kb
Host	smart-b15b826a-a701-481c-9136-1e8e769e6a63
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394191079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1 394191079
Directory	/workspace/5.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4143806008
Short name	T35
Test name
Test status
Simulation time	1242894516 ps
CPU time	4.08 seconds
Started	Dec 20 12:32:43 PM PST 23
Finished	Dec 20 12:33:30 PM PST 23
Peak memory	215604 kb
Host	smart-6bf34ca4-11ec-4a33-a4b8-d881e0538939
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143806008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s pi_device_same_csr_outstanding.4143806008
Directory	/workspace/5.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3727607420
Short name	T123
Test name
Test status
Simulation time	64298022 ps
CPU time	4.28 seconds
Started	Dec 20 12:32:33 PM PST 23
Finished	Dec 20 12:33:20 PM PST 23
Peak memory	216192 kb
Host	smart-6a489f98-dda1-4886-9cc9-f496b11605f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727607420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3 727607420
Directory	/workspace/5.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2673438760
Short name	T51
Test name
Test status
Simulation time	1118075502 ps
CPU time	21.95 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:36 PM PST 23
Peak memory	215756 kb
Host	smart-488d2661-680b-4741-85cd-bc0e26a094c4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673438760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device _tl_intg_err.2673438760
Directory	/workspace/5.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1341058317
Short name	T157
Test name
Test status
Simulation time	72683819 ps
CPU time	1.19 seconds
Started	Dec 20 12:34:12 PM PST 23
Finished	Dec 20 12:34:19 PM PST 23
Peak memory	215820 kb
Host	smart-477ce355-7c17-414d-a3d1-4af1fc6d3bcf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341058317 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1341058317
Directory	/workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3837045169
Short name	T128
Test name
Test status
Simulation time	886838189 ps
CPU time	2.53 seconds
Started	Dec 20 12:32:36 PM PST 23
Finished	Dec 20 12:33:22 PM PST 23
Peak memory	215720 kb
Host	smart-d72eacff-6c93-4a5f-b750-258d676aff76
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837045169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3 837045169
Directory	/workspace/6.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.157488197
Short name	T81
Test name
Test status
Simulation time	20087044 ps
CPU time	0.68 seconds
Started	Dec 20 12:34:34 PM PST 23
Finished	Dec 20 12:34:43 PM PST 23
Peak memory	204692 kb
Host	smart-3a51d5d9-8368-42d0-b4ba-e547ebaa6e4b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157488197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.157488197
Directory	/workspace/6.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3718126895
Short name	T104
Test name
Test status
Simulation time	79547265 ps
CPU time	1.69 seconds
Started	Dec 20 12:32:58 PM PST 23
Finished	Dec 20 12:33:48 PM PST 23
Peak memory	215684 kb
Host	smart-62afc80f-e901-4a34-ad8a-30f11ef175a5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718126895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s pi_device_same_csr_outstanding.3718126895
Directory	/workspace/6.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2706002169
Short name	T108
Test name
Test status
Simulation time	436113894 ps
CPU time	3.92 seconds
Started	Dec 20 12:32:39 PM PST 23
Finished	Dec 20 12:33:27 PM PST 23
Peak memory	215896 kb
Host	smart-3e94ddff-72d1-427c-8d84-9b3118fc1eb3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706002169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2 706002169
Directory	/workspace/6.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4235475418
Short name	T102
Test name
Test status
Simulation time	98408200 ps
CPU time	1.26 seconds
Started	Dec 20 12:32:42 PM PST 23
Finished	Dec 20 12:33:26 PM PST 23
Peak memory	217260 kb
Host	smart-68f2e4e2-e303-44f3-bb4d-8dd9ad4e998c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235475418 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4235475418
Directory	/workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4017478989
Short name	T155
Test name
Test status
Simulation time	95899781 ps
CPU time	1.63 seconds
Started	Dec 20 12:33:55 PM PST 23
Finished	Dec 20 12:34:17 PM PST 23
Peak memory	214420 kb
Host	smart-f2a1813e-f499-420c-82b6-c6ce8d140cc3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017478989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4 017478989
Directory	/workspace/7.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.816991097
Short name	T83
Test name
Test status
Simulation time	12517129 ps
CPU time	0.71 seconds
Started	Dec 20 12:34:11 PM PST 23
Finished	Dec 20 12:34:19 PM PST 23
Peak memory	204356 kb
Host	smart-847f6dab-4e5f-4dc9-bf48-d26d0b2a4bea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816991097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.816991097
Directory	/workspace/7.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2180130723
Short name	T43
Test name
Test status
Simulation time	241503980 ps
CPU time	2.9 seconds
Started	Dec 20 12:32:37 PM PST 23
Finished	Dec 20 12:33:24 PM PST 23
Peak memory	215860 kb
Host	smart-86c76025-4b02-424d-a133-b34b152b8d9b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180130723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s pi_device_same_csr_outstanding.2180130723
Directory	/workspace/7.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3890054419
Short name	T18
Test name
Test status
Simulation time	299345296 ps
CPU time	5.92 seconds
Started	Dec 20 12:34:12 PM PST 23
Finished	Dec 20 12:34:24 PM PST 23
Peak memory	215456 kb
Host	smart-42055c28-2808-40ee-bd6e-e508e0d1579b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890054419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3 890054419
Directory	/workspace/7.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3872255390
Short name	T23
Test name
Test status
Simulation time	4423689461 ps
CPU time	22.24 seconds
Started	Dec 20 12:34:11 PM PST 23
Finished	Dec 20 12:34:40 PM PST 23
Peak memory	216296 kb
Host	smart-fb881441-a9ae-4f3b-b10a-8a0e21eb96ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872255390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device _tl_intg_err.3872255390
Directory	/workspace/7.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3664556931
Short name	T4
Test name
Test status
Simulation time	12445511 ps
CPU time	1.2 seconds
Started	Dec 20 12:33:05 PM PST 23
Finished	Dec 20 12:33:56 PM PST 23
Peak memory	217136 kb
Host	smart-08de28a2-82bc-43dc-818c-c888dcdd799d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664556931 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3664556931
Directory	/workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2756066633
Short name	T25
Test name
Test status
Simulation time	60284321 ps
CPU time	1.15 seconds
Started	Dec 20 12:32:35 PM PST 23
Finished	Dec 20 12:33:19 PM PST 23
Peak memory	207632 kb
Host	smart-43fc66f2-1d07-4b41-ad2d-cbee6d853c28
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756066633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2 756066633
Directory	/workspace/8.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.3849366024
Short name	T76
Test name
Test status
Simulation time	55021133 ps
CPU time	0.7 seconds
Started	Dec 20 12:32:34 PM PST 23
Finished	Dec 20 12:33:17 PM PST 23
Peak memory	204820 kb
Host	smart-c255c9a0-c577-4b30-8492-2463893f949d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849366024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3 849366024
Directory	/workspace/8.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1779406315
Short name	T159
Test name
Test status
Simulation time	160309621 ps
CPU time	1.98 seconds
Started	Dec 20 12:32:30 PM PST 23
Finished	Dec 20 12:33:15 PM PST 23
Peak memory	215752 kb
Host	smart-99bd9485-101d-4cdd-a34e-5216fabdf094
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779406315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s pi_device_same_csr_outstanding.1779406315
Directory	/workspace/8.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2532823359
Short name	T169
Test name
Test status
Simulation time	4636848938 ps
CPU time	6.37 seconds
Started	Dec 20 12:32:27 PM PST 23
Finished	Dec 20 12:33:17 PM PST 23
Peak memory	216176 kb
Host	smart-87628520-6601-41e2-81b4-72aa09d90029
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532823359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2 532823359
Directory	/workspace/8.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1838040111
Short name	T26
Test name
Test status
Simulation time	271403842 ps
CPU time	13.07 seconds
Started	Dec 20 12:32:54 PM PST 23
Finished	Dec 20 12:33:55 PM PST 23
Peak memory	215880 kb
Host	smart-f5541e03-3809-4238-8041-4a96fd08971f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838040111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device _tl_intg_err.1838040111
Directory	/workspace/8.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2217806632
Short name	T127
Test name
Test status
Simulation time	71777307 ps
CPU time	2.16 seconds
Started	Dec 20 12:32:32 PM PST 23
Finished	Dec 20 12:33:18 PM PST 23
Peak memory	217904 kb
Host	smart-ec0d4c5a-9938-4463-b24b-4fc23062a868
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217806632 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2217806632
Directory	/workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3165185
Short name	T166
Test name
Test status
Simulation time	189777474 ps
CPU time	2.09 seconds
Started	Dec 20 12:32:46 PM PST 23
Finished	Dec 20 12:33:33 PM PST 23
Peak memory	215900 kb
Host	smart-11633ca4-cf60-4ce3-84b9-26e5cf175285
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3165185
Directory	/workspace/9.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.579585546
Short name	T145
Test name
Test status
Simulation time	43670858 ps
CPU time	0.71 seconds
Started	Dec 20 12:32:38 PM PST 23
Finished	Dec 20 12:33:22 PM PST 23
Peak memory	204912 kb
Host	smart-cda39f7b-53dd-4e30-a6a1-1cf840d9939d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579585546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.579585546
Directory	/workspace/9.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3713783177
Short name	T158
Test name
Test status
Simulation time	319032239 ps
CPU time	3.35 seconds
Started	Dec 20 12:32:31 PM PST 23
Finished	Dec 20 12:33:18 PM PST 23
Peak memory	215860 kb
Host	smart-f21cd46a-09f2-4846-8038-07e50a1d7b0d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713783177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s pi_device_same_csr_outstanding.3713783177
Directory	/workspace/9.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2329509824
Short name	T165
Test name
Test status
Simulation time	350389814 ps
CPU time	4.47 seconds
Started	Dec 20 12:34:28 PM PST 23
Finished	Dec 20 12:34:33 PM PST 23
Peak memory	215784 kb
Host	smart-2b8bbd5d-4ddb-4e4d-a9ba-0affc7a7dbe5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329509824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2 329509824
Directory	/workspace/9.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1491990395
Short name	T162
Test name
Test status
Simulation time	1322639037 ps
CPU time	7.57 seconds
Started	Dec 20 12:33:14 PM PST 23
Finished	Dec 20 12:34:09 PM PST 23
Peak memory	215864 kb
Host	smart-c235088a-4f4f-45a7-a2d5-54051ea88eb0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491990395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device _tl_intg_err.1491990395
Directory	/workspace/9.spi_device_tl_intg_err/latest