Summary for Variable cp_is_write
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
2 |
2 |
0 |
0.00 |
User Defined Bins for cp_is_write
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| read |
0 |
1 |
1 |
|
| write |
0 |
1 |
1 |
|
Summary for Variable cp_payload_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
7 |
7 |
0 |
0.00 |
User Defined Bins for cp_payload_size
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| excess_fifo |
0 |
1 |
1 |
|
| frequent_use_values[0] |
0 |
1 |
1 |
|
| frequent_use_values[1] |
0 |
1 |
1 |
|
| frequent_use_values[2] |
0 |
1 |
1 |
|
| frequent_use_values[3] |
0 |
1 |
1 |
|
| frequent_use_values[4] |
0 |
1 |
1 |
|
| frequent_use_values[256] |
0 |
1 |
1 |
|
Summary for Cross cr_all
Samples crossed: cp_is_write cp_payload_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
8 |
8 |
0 |
0.00 |
8 |
| Automatically Generated Cross Bins |
8 |
8 |
0 |
0.00 |
8 |
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cr_all
Element holes
| cp_is_write | cp_payload_size | COUNT | AT LEAST | NUMBER | STATUS |
| [write] |
* |
-- |
-- |
7 |
|
Uncovered bins
| cp_is_write | cp_payload_size | COUNT | AT LEAST | NUMBER | STATUS |
| [read] |
[frequent_use_values[0]] |
0 |
1 |
1 |
|
User Defined Cross Bins for cr_all
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| read_w_nonzero_payload |
0 |
Illegal |