Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	12	0	12	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	425	1			T2	1		T3	11		T9	1
all_pins[1]	425	1			T2	1		T3	11		T9	1
all_pins[2]	425	1			T2	1		T3	11		T9	1
all_pins[3]	425	1			T2	1		T3	11		T9	1
all_pins[4]	425	1			T2	1		T3	11		T9	1
all_pins[5]	425	1			T2	1		T3	11		T9	1
all_pins[6]	425	1			T2	1		T3	11		T9	1
all_pins[7]	425	1			T2	1		T3	11		T9	1
all_pins[8]	425	1			T2	1		T3	11		T9	1
all_pins[9]	425	1			T2	1		T3	11		T9	1
all_pins[10]	425	1			T2	1		T3	11		T9	1
all_pins[11]	425	1			T2	1		T3	11		T9	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4060	1			T2	12		T3	110		T9	12
values[0x1]	1040	1			T3	22		T7	6		T8	28
transitions[0x0=>0x1]	760	1			T3	16		T7	3		T8	23
transitions[0x1=>0x0]	771	1			T3	16		T7	4		T8	23

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	338	1			T2	1		T3	9		T9	1
all_pins[0]	values[0x1]	87	1			T3	2		T8	4		T13	2
all_pins[0]	transitions[0x0=>0x1]	63	1			T3	2		T8	4		T13	2
all_pins[0]	transitions[0x1=>0x0]	55	1			T8	2		T14	1		T28	1
all_pins[1]	values[0x0]	346	1			T2	1		T3	11		T9	1
all_pins[1]	values[0x1]	79	1			T8	2		T14	2		T28	1
all_pins[1]	transitions[0x0=>0x1]	57	1			T8	2		T14	1		T28	1
all_pins[1]	transitions[0x1=>0x0]	65	1			T3	2		T7	1		T13	1
all_pins[2]	values[0x0]	338	1			T2	1		T3	9		T9	1
all_pins[2]	values[0x1]	87	1			T3	2		T7	1		T13	1
all_pins[2]	transitions[0x0=>0x1]	68	1			T3	2		T7	1		T13	1
all_pins[2]	transitions[0x1=>0x0]	62	1			T7	2		T8	3		T14	4
all_pins[3]	values[0x0]	344	1			T2	1		T3	11		T9	1
all_pins[3]	values[0x1]	81	1			T7	2		T8	3		T14	4
all_pins[3]	transitions[0x0=>0x1]	55	1			T8	2		T14	4		T28	3
all_pins[3]	transitions[0x1=>0x0]	78	1			T3	2		T8	2		T13	1
all_pins[4]	values[0x0]	321	1			T2	1		T3	9		T9	1
all_pins[4]	values[0x1]	104	1			T3	2		T7	2		T8	3
all_pins[4]	transitions[0x0=>0x1]	82	1			T7	2		T8	3		T13	1
all_pins[4]	transitions[0x1=>0x0]	68	1			T3	5		T8	3		T14	1
all_pins[5]	values[0x0]	335	1			T2	1		T3	4		T9	1
all_pins[5]	values[0x1]	90	1			T3	7		T8	3		T14	1
all_pins[5]	transitions[0x0=>0x1]	61	1			T3	6		T8	3		T14	1
all_pins[5]	transitions[0x1=>0x0]	79	1			T8	2		T13	2		T14	2
all_pins[6]	values[0x0]	317	1			T2	1		T3	10		T9	1
all_pins[6]	values[0x1]	108	1			T3	1		T8	2		T13	2
all_pins[6]	transitions[0x0=>0x1]	77	1			T3	1		T8	1		T13	2
all_pins[6]	transitions[0x1=>0x0]	57	1			T3	1		T8	3		T14	2
all_pins[7]	values[0x0]	337	1			T2	1		T3	10		T9	1
all_pins[7]	values[0x1]	88	1			T3	1		T8	4		T14	2
all_pins[7]	transitions[0x0=>0x1]	63	1			T8	4		T14	2		T28	2
all_pins[7]	transitions[0x1=>0x0]	52	1			T13	1		T14	2		T28	1
all_pins[8]	values[0x0]	348	1			T2	1		T3	10		T9	1
all_pins[8]	values[0x1]	77	1			T3	1		T13	1		T14	2
all_pins[8]	transitions[0x0=>0x1]	58	1			T13	1		T14	2		T28	1
all_pins[8]	transitions[0x1=>0x0]	73	1			T3	2		T8	2		T13	3
all_pins[9]	values[0x0]	333	1			T2	1		T3	8		T9	1
all_pins[9]	values[0x1]	92	1			T3	3		T8	2		T13	3
all_pins[9]	transitions[0x0=>0x1]	68	1			T3	3		T8	2		T14	1
all_pins[9]	transitions[0x1=>0x0]	53	1			T3	1		T8	2		T14	2
all_pins[10]	values[0x0]	348	1			T2	1		T3	10		T9	1
all_pins[10]	values[0x1]	77	1			T3	1		T8	2		T13	3
all_pins[10]	transitions[0x0=>0x1]	66	1			T3	1		T13	3		T14	2
all_pins[10]	transitions[0x1=>0x0]	59	1			T3	2		T7	1		T8	1
all_pins[11]	values[0x0]	355	1			T2	1		T3	9		T9	1
all_pins[11]	values[0x1]	70	1			T3	2		T7	1		T8	3
all_pins[11]	transitions[0x0=>0x1]	42	1			T3	1		T8	2		T44	2
all_pins[11]	transitions[0x1=>0x0]	70	1			T3	1		T8	3		T13	2