Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	72	2	70	97.22

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	72	2	70	97.22	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	356	1			T3	10		T7	4		T8	10
all_values[1]	356	1			T3	10		T7	4		T8	10
all_values[2]	356	1			T3	10		T7	4		T8	10
all_values[3]	356	1			T3	10		T7	4		T8	10
all_values[4]	356	1			T3	10		T7	4		T8	10
all_values[5]	356	1			T3	10		T7	4		T8	10
all_values[6]	356	1			T3	10		T7	4		T8	10
all_values[7]	356	1			T3	10		T7	4		T8	10
all_values[8]	356	1			T3	10		T7	4		T8	10
all_values[9]	356	1			T3	10		T7	4		T8	10
all_values[10]	356	1			T3	10		T7	4		T8	10
all_values[11]	356	1			T3	10		T7	4		T8	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2259

1

T3

64

T7

22

T8

56

auto[1]

2013

1

T3

56

T7

26

T8

64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1692

1

T3

48

T7

34

T8

56

auto[1]

2580

1

T3

72

T7

14

T8

64

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2443

1

T3

61

T7

36

T8

74

auto[1]

1829

1

T3

59

T7

12

T8

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	2	70	97.22	2
Automatically Generated Cross Bins	72	2	70	97.22	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[11]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	76	1			T3	2		T7	2		T8	2
all_values[0]	auto[0]	auto[0]	auto[1]	31	1			T14	3		T28	2		T56	1
all_values[0]	auto[0]	auto[1]	auto[0]	63	1			T3	2		T7	2		T8	1
all_values[0]	auto[0]	auto[1]	auto[1]	34	1			T8	1		T13	1		T14	1
all_values[0]	auto[1]	auto[0]	auto[1]	74	1			T3	3		T8	2		T14	5
all_values[0]	auto[1]	auto[1]	auto[1]	78	1			T3	3		T8	4		T13	1
all_values[1]	auto[0]	auto[0]	auto[0]	70	1			T3	1		T8	1		T13	3
all_values[1]	auto[0]	auto[0]	auto[1]	37	1			T3	2		T8	2		T14	1
all_values[1]	auto[0]	auto[1]	auto[0]	82	1			T3	4		T7	2		T8	1
all_values[1]	auto[0]	auto[1]	auto[1]	30	1			T8	2		T60	2		T61	2
all_values[1]	auto[1]	auto[0]	auto[1]	79	1			T3	1		T7	2		T8	4
all_values[1]	auto[1]	auto[1]	auto[1]	58	1			T3	2		T14	2		T28	2
all_values[2]	auto[0]	auto[0]	auto[0]	73	1			T7	2		T8	4		T14	1
all_values[2]	auto[0]	auto[0]	auto[1]	31	1			T3	2		T8	1		T13	1
all_values[2]	auto[0]	auto[1]	auto[0]	49	1			T3	1		T8	4		T14	2
all_values[2]	auto[0]	auto[1]	auto[1]	37	1			T13	1		T14	1		T44	1
all_values[2]	auto[1]	auto[0]	auto[1]	96	1			T3	4		T8	1		T13	2
all_values[2]	auto[1]	auto[1]	auto[1]	70	1			T3	3		T7	2		T14	1
all_values[3]	auto[0]	auto[0]	auto[0]	77	1			T3	6		T7	1		T13	2
all_values[3]	auto[0]	auto[0]	auto[1]	38	1			T3	1		T8	2		T28	1
all_values[3]	auto[0]	auto[1]	auto[0]	49	1			T8	2		T14	4		T28	1
all_values[3]	auto[0]	auto[1]	auto[1]	30	1			T7	1		T8	1		T14	2
all_values[3]	auto[1]	auto[0]	auto[1]	79	1			T3	3		T7	1		T13	1
all_values[3]	auto[1]	auto[1]	auto[1]	83	1			T7	1		T8	5		T13	1
all_values[4]	auto[0]	auto[0]	auto[0]	69	1			T3	2		T8	2		T14	7
all_values[4]	auto[0]	auto[0]	auto[1]	33	1			T28	3		T44	1		T56	1
all_values[4]	auto[0]	auto[1]	auto[0]	47	1			T3	2		T8	1		T13	2
all_values[4]	auto[0]	auto[1]	auto[1]	41	1			T3	1		T7	1		T8	2
all_values[4]	auto[1]	auto[0]	auto[1]	79	1			T3	5		T8	2		T13	2
all_values[4]	auto[1]	auto[1]	auto[1]	87	1			T7	3		T8	3		T44	2
all_values[5]	auto[0]	auto[0]	auto[0]	61	1			T8	2		T13	1		T14	2
all_values[5]	auto[0]	auto[0]	auto[1]	35	1			T8	1		T14	1		T28	3
all_values[5]	auto[0]	auto[1]	auto[0]	69	1			T7	3		T8	2		T13	2
all_values[5]	auto[0]	auto[1]	auto[1]	33	1			T3	2		T8	1		T28	3
all_values[5]	auto[1]	auto[0]	auto[1]	78	1			T3	3		T13	1		T14	3
all_values[5]	auto[1]	auto[1]	auto[1]	80	1			T3	5		T7	1		T8	4
all_values[6]	auto[0]	auto[0]	auto[0]	70	1			T3	2		T7	4		T8	2
all_values[6]	auto[0]	auto[0]	auto[1]	22	1			T8	1		T14	2		T28	1
all_values[6]	auto[0]	auto[1]	auto[0]	63	1			T3	4		T8	4		T14	1
all_values[6]	auto[0]	auto[1]	auto[1]	51	1			T3	1		T8	1		T13	1
all_values[6]	auto[1]	auto[0]	auto[1]	74	1			T3	2		T14	4		T28	4
all_values[6]	auto[1]	auto[1]	auto[1]	76	1			T3	1		T8	2		T13	1
all_values[7]	auto[0]	auto[0]	auto[0]	80	1			T3	3		T7	2		T8	1
all_values[7]	auto[0]	auto[0]	auto[1]	32	1			T3	1		T14	4		T61	2
all_values[7]	auto[0]	auto[1]	auto[0]	64	1			T7	2		T8	2		T28	1
all_values[7]	auto[0]	auto[1]	auto[1]	35	1			T28	1		T56	1		T58	1
all_values[7]	auto[1]	auto[0]	auto[1]	76	1			T3	2		T8	3		T13	1
all_values[7]	auto[1]	auto[1]	auto[1]	69	1			T3	4		T8	4		T44	1
all_values[8]	auto[0]	auto[0]	auto[0]	86	1			T3	3		T7	1		T8	4
all_values[8]	auto[0]	auto[0]	auto[1]	28	1			T8	1		T14	1		T56	2
all_values[8]	auto[0]	auto[1]	auto[0]	59	1			T3	2		T7	2		T8	3
all_values[8]	auto[0]	auto[1]	auto[1]	36	1			T13	1		T14	1		T28	1
all_values[8]	auto[1]	auto[0]	auto[1]	79	1			T7	1		T8	1		T13	1
all_values[8]	auto[1]	auto[1]	auto[1]	68	1			T3	5		T8	1		T14	3
all_values[9]	auto[0]	auto[0]	auto[0]	87	1			T3	2		T7	2		T8	3
all_values[9]	auto[0]	auto[0]	auto[1]	35	1			T13	1		T14	1		T28	1
all_values[9]	auto[0]	auto[1]	auto[0]	54	1			T3	2		T7	2		T8	4
all_values[9]	auto[0]	auto[1]	auto[1]	34	1			T3	1		T8	1		T13	1
all_values[9]	auto[1]	auto[0]	auto[1]	78	1			T3	3		T8	1		T13	1
all_values[9]	auto[1]	auto[1]	auto[1]	68	1			T3	2		T8	1		T13	1
all_values[10]	auto[0]	auto[0]	auto[0]	68	1			T3	2		T7	4		T8	1
all_values[10]	auto[0]	auto[0]	auto[1]	31	1			T3	1		T8	1		T14	1
all_values[10]	auto[0]	auto[1]	auto[0]	67	1			T3	3		T8	5		T14	2
all_values[10]	auto[0]	auto[1]	auto[1]	37	1			T3	1		T13	2		T14	1
all_values[10]	auto[1]	auto[0]	auto[1]	92	1			T3	2		T8	2		T13	2
all_values[10]	auto[1]	auto[1]	auto[1]	61	1			T3	1		T8	1		T14	1
all_values[11]	auto[0]	auto[0]	auto[0]	120	1			T3	3		T8	5		T13	2
all_values[11]	auto[0]	auto[1]	auto[0]	89	1			T3	2		T7	3		T14	4
all_values[11]	auto[1]	auto[0]	auto[1]	85	1			T3	3		T8	4		T13	2
all_values[11]	auto[1]	auto[1]	auto[1]	62	1			T3	2		T7	1		T8	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal