Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6539028	1			T1	2		T4	1		T2	2
all_values[1]	6539028	1			T1	2		T4	1		T2	2
all_values[2]	6539028	1			T1	2		T4	1		T2	2
all_values[3]	6539028	1			T1	2		T4	1		T2	2
all_values[4]	6539028	1			T1	2		T4	1		T2	2
all_values[5]	6539028	1			T1	2		T4	1		T2	2
all_values[6]	6539028	1			T1	2		T4	1		T2	2
all_values[7]	6539028	1			T1	2		T4	1		T2	2
all_values[8]	6539028	1			T1	2		T4	1		T2	2
all_values[9]	6539028	1			T1	2		T4	1		T2	2
all_values[10]	6539028	1			T1	2		T4	1		T2	2
all_values[11]	6539028	1			T1	2		T4	1		T2	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76213201

1

T1

14

T4

12

T2

18

auto[1]

2255135

1

T1

10

T2

6

T5

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78409371

1

T1

24

T4

12

T2

24

auto[1]

58965

1

T83

57

T84

22

T85

72

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6287145	1			T1	2		T4	1		T5	2
all_values[0]	auto[0]	auto[1]	111	1			T83	2		T84	1		T85	5
all_values[0]	auto[1]	auto[0]	251648	1			T2	2		T9	2		T18	2
all_values[0]	auto[1]	auto[1]	124	1			T83	4		T85	3		T164	2
all_values[1]	auto[0]	auto[0]	6324578	1			T4	1		T2	2		T5	2
all_values[1]	auto[0]	auto[1]	96	1			T212	2		T199	2		T200	2
all_values[1]	auto[1]	auto[0]	214237	1			T1	2		T9	5		T83	6
all_values[1]	auto[1]	auto[1]	117	1			T83	4		T84	1		T85	3
all_values[2]	auto[0]	auto[0]	6371708	1			T1	2		T4	1		T2	2
all_values[2]	auto[0]	auto[1]	118	1			T85	3		T86	3		T212	3
all_values[2]	auto[1]	auto[0]	167087	1			T9	2		T16	2		T19	2
all_values[2]	auto[1]	auto[1]	115	1			T83	2		T84	1		T85	5
all_values[3]	auto[0]	auto[0]	6270811	1			T1	2		T4	1		T5	2
all_values[3]	auto[0]	auto[1]	127	1			T83	3		T84	3		T85	1
all_values[3]	auto[1]	auto[0]	267965	1			T2	2		T9	2		T16	2
all_values[3]	auto[1]	auto[1]	125	1			T83	4		T84	1		T85	1
all_values[4]	auto[0]	auto[0]	6188968	1			T1	2		T4	1		T5	2
all_values[4]	auto[0]	auto[1]	105	1			T83	2		T84	3		T85	2
all_values[4]	auto[1]	auto[0]	349846	1			T2	2		T9	5		T83	5
all_values[4]	auto[1]	auto[1]	109	1			T83	1		T85	6		T86	4
all_values[5]	auto[0]	auto[0]	6441685	1			T4	1		T2	2		T9	4
all_values[5]	auto[0]	auto[1]	105	1			T83	4		T85	4		T86	2
all_values[5]	auto[1]	auto[0]	97111	1			T1	2		T5	2		T9	2
all_values[5]	auto[1]	auto[1]	127	1			T83	3		T84	1		T85	2
all_values[6]	auto[0]	auto[0]	6362167	1			T4	1		T2	2		T5	2
all_values[6]	auto[0]	auto[1]	33195	1			T84	3		T85	3		T86	2
all_values[6]	auto[1]	auto[0]	142968	1			T1	2		T9	2		T10	2
all_values[6]	auto[1]	auto[1]	698	1			T85	3		T86	1		T212	3
all_values[7]	auto[0]	auto[0]	6434349	1			T1	2		T4	1		T2	2
all_values[7]	auto[0]	auto[1]	16364	1			T83	3		T85	3		T164	1
all_values[7]	auto[1]	auto[0]	88057	1			T9	3		T10	2		T19	2
all_values[7]	auto[1]	auto[1]	258	1			T83	3		T84	1		T85	6
all_values[8]	auto[0]	auto[0]	6387551	1			T1	2		T4	1		T2	2
all_values[8]	auto[0]	auto[1]	6077	1			T83	2		T84	2		T85	5
all_values[8]	auto[1]	auto[0]	145287	1			T9	2		T10	2		T16	2
all_values[8]	auto[1]	auto[1]	113	1			T83	1		T85	3		T86	3
all_values[9]	auto[0]	auto[0]	6487796	1			T4	1		T2	2		T9	6
all_values[9]	auto[0]	auto[1]	136	1			T83	2		T85	1		T86	1
all_values[9]	auto[1]	auto[0]	50991	1			T1	2		T5	2		T18	2
all_values[9]	auto[1]	auto[1]	105	1			T83	5		T85	4		T86	1
all_values[10]	auto[0]	auto[0]	6274223	1			T4	1		T2	2		T5	2
all_values[10]	auto[0]	auto[1]	131	1			T83	4		T84	3		T85	1
all_values[10]	auto[1]	auto[0]	264574	1			T1	2		T9	2		T10	2
all_values[10]	auto[1]	auto[1]	100	1			T83	2		T84	1		T85	2
all_values[11]	auto[0]	auto[0]	6325347	1			T1	2		T4	1		T2	2
all_values[11]	auto[0]	auto[1]	308	1			T83	2		T84	1		T85	2
all_values[11]	auto[1]	auto[0]	213272	1			T9	2		T10	2		T16	2
all_values[11]	auto[1]	auto[1]	101	1			T83	4		T85	4		T86	2