Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.10 99.01 96.33 98.63 92.06 98.05 95.86 99.76


Total tests in report: 1747
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
58.28 58.28 91.53 91.53 77.95 77.95 58.61 58.61 14.75 14.75 87.42 87.42 71.05 71.05 6.67 6.67 /workspace/coverage/default/37.spi_device_upload.1474535311
72.70 14.42 95.23 3.70 83.81 5.86 63.80 5.19 68.85 54.10 92.85 5.44 80.80 9.75 23.58 16.91 /workspace/coverage/default/20.spi_device_stress_all.1879990714
79.40 6.70 97.41 2.18 88.82 5.01 70.35 6.56 86.89 18.03 96.02 3.17 84.49 3.69 31.82 8.24 /workspace/coverage/default/16.spi_device_stress_all.40532502
84.60 5.20 98.29 0.88 92.96 4.14 89.43 19.08 86.89 0.00 97.17 1.15 93.80 9.31 33.64 1.81 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3136597690
87.99 3.39 98.46 0.17 93.38 0.42 89.43 0.00 90.16 3.28 97.43 0.25 93.94 0.15 53.12 19.49 /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1341449755
89.36 1.37 98.48 0.02 93.40 0.03 89.43 0.00 90.16 0.00 97.46 0.03 93.94 0.00 62.60 9.48 /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3726265360
90.69 1.34 98.72 0.23 93.82 0.42 92.37 2.94 90.16 0.00 97.46 0.00 93.94 0.00 68.37 5.76 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3481639661
91.92 1.23 98.72 0.00 93.82 0.00 92.37 0.00 90.16 0.00 97.46 0.00 93.94 0.00 76.94 8.58 /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3297617564
92.75 0.83 98.77 0.06 93.87 0.05 92.37 0.00 93.44 3.28 97.53 0.07 93.94 0.00 79.32 2.38 /workspace/coverage/default/1.spi_device_flash_and_tpm.3527065161
93.31 0.56 98.78 0.01 93.87 0.00 92.37 0.00 93.44 0.00 97.54 0.02 93.94 0.00 83.23 3.91 /workspace/coverage/default/21.spi_device_stress_all.1192989345
93.87 0.56 98.79 0.01 93.87 0.00 96.28 3.91 93.44 0.00 97.54 0.00 93.94 0.00 83.23 0.00 /workspace/coverage/default/1.spi_device_ram_cfg.1078194922
94.25 0.38 98.79 0.00 93.88 0.01 96.28 0.00 93.44 0.00 97.56 0.02 93.94 0.00 85.85 2.62 /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2189376067
94.63 0.38 98.87 0.07 94.68 0.80 96.87 0.59 93.44 0.00 97.58 0.02 94.24 0.30 86.71 0.86 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.425950560
94.90 0.27 98.89 0.03 94.72 0.04 96.87 0.00 93.44 0.00 97.65 0.07 94.24 0.00 88.47 1.76 /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3121161510
95.17 0.27 99.01 0.11 95.18 0.46 96.87 0.00 93.44 0.00 97.80 0.15 94.83 0.59 89.04 0.57 /workspace/coverage/default/42.spi_device_flash_mode.1378691658
95.43 0.27 99.04 0.04 95.27 0.09 96.87 0.00 95.08 1.64 97.85 0.05 94.83 0.00 89.09 0.05 /workspace/coverage/default/19.spi_device_rx_timeout.622386627
95.66 0.22 99.06 0.02 95.84 0.57 97.06 0.20 95.08 0.00 97.87 0.02 94.83 0.00 89.85 0.76 /workspace/coverage/default/17.spi_device_stress_all.4184558724
95.87 0.21 99.06 0.00 95.84 0.00 97.65 0.59 95.08 0.00 97.87 0.00 95.72 0.89 89.85 0.00 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2792582642
96.04 0.17 99.06 0.00 95.84 0.00 97.65 0.00 95.08 0.00 97.87 0.00 95.72 0.00 91.04 1.19 /workspace/coverage/default/6.spi_device_flash_and_tpm.4171245783
96.18 0.14 99.06 0.00 95.84 0.00 97.65 0.00 95.08 0.00 97.87 0.00 95.72 0.00 92.04 1.00 /workspace/coverage/default/37.spi_device_flash_all.1087578271
96.30 0.12 99.06 0.00 95.84 0.00 97.85 0.20 95.08 0.00 97.87 0.00 95.72 0.00 92.71 0.67 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1411668865
96.43 0.12 99.06 0.00 95.84 0.00 97.85 0.00 95.08 0.00 97.87 0.00 95.72 0.00 93.57 0.86 /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2085800478
96.54 0.12 99.10 0.04 95.86 0.03 97.85 0.00 95.08 0.00 97.92 0.05 95.72 0.00 94.28 0.71 /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2444898485
96.66 0.12 99.10 0.00 95.86 0.00 97.85 0.00 95.08 0.00 97.92 0.00 95.72 0.00 95.09 0.81 /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.904951086
96.75 0.09 99.10 0.00 95.89 0.03 98.24 0.39 95.08 0.00 97.92 0.00 95.86 0.15 95.19 0.10 /workspace/coverage/default/0.spi_device_sec_cm.692799575
96.84 0.09 99.10 0.00 95.89 0.00 98.24 0.00 95.08 0.00 97.92 0.00 95.86 0.00 95.81 0.62 /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.855292520
96.91 0.07 99.10 0.00 95.89 0.00 98.24 0.00 95.08 0.00 97.92 0.00 95.86 0.00 96.28 0.48 /workspace/coverage/default/43.spi_device_flash_and_tpm.197293558
96.97 0.06 99.10 0.00 95.89 0.00 98.63 0.39 95.08 0.00 97.92 0.00 95.86 0.00 96.33 0.05 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.826233878
97.03 0.06 99.10 0.00 95.89 0.00 98.63 0.00 95.08 0.00 97.92 0.00 95.86 0.00 96.76 0.43 /workspace/coverage/default/16.spi_device_bit_transfer.4270136931
97.08 0.04 99.10 0.00 95.89 0.00 98.63 0.00 95.08 0.00 97.92 0.00 95.86 0.00 97.05 0.29 /workspace/coverage/default/17.spi_device_flash_and_tpm.55971790
97.11 0.03 99.10 0.00 95.89 0.00 98.63 0.00 95.08 0.00 97.92 0.00 95.86 0.00 97.28 0.24 /workspace/coverage/default/14.spi_device_flash_all.937754718
97.14 0.03 99.16 0.06 95.98 0.09 98.63 0.00 95.08 0.00 98.00 0.08 95.86 0.00 97.28 0.00 /workspace/coverage/default/1.spi_device_mem_parity.3259735915
97.17 0.03 99.16 0.00 95.98 0.00 98.63 0.00 95.08 0.00 98.02 0.02 95.86 0.00 97.47 0.19 /workspace/coverage/default/15.spi_device_extreme_fifo_size.201794949
97.20 0.03 99.16 0.00 96.18 0.20 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 97.47 0.00 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.625252519
97.23 0.03 99.16 0.00 96.18 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 97.67 0.19 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.142279134
97.26 0.03 99.16 0.00 96.18 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 97.86 0.19 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1321041276
97.28 0.03 99.16 0.00 96.18 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.05 0.19 /workspace/coverage/default/14.spi_device_flash_and_tpm.3675277016
97.30 0.02 99.16 0.00 96.18 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.19 0.14 /workspace/coverage/default/20.spi_device_flash_and_tpm.4020487117
97.32 0.02 99.16 0.00 96.18 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.33 0.14 /workspace/coverage/default/32.spi_device_stress_all.1443392501
97.34 0.02 99.16 0.00 96.18 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.48 0.14 /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.176543523
97.36 0.02 99.16 0.00 96.18 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.62 0.14 /workspace/coverage/default/45.spi_device_flash_and_tpm.657885890
97.38 0.02 99.16 0.00 96.19 0.01 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.71 0.10 /workspace/coverage/default/15.spi_device_stress_all.2836500752
97.39 0.01 99.16 0.00 96.19 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.81 0.10 /workspace/coverage/default/10.spi_device_extreme_fifo_size.3739355981
97.41 0.01 99.16 0.00 96.19 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.90 0.10 /workspace/coverage/default/28.spi_device_extreme_fifo_size.2655663392
97.42 0.01 99.16 0.00 96.19 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.00 0.10 /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4288666203
97.43 0.01 99.16 0.00 96.19 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.09 0.10 /workspace/coverage/default/29.spi_device_flash_mode.3231923193
97.45 0.01 99.16 0.00 96.19 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.19 0.10 /workspace/coverage/default/41.spi_device_flash_all.1879875318
97.46 0.01 99.16 0.00 96.19 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.29 0.10 /workspace/coverage/default/49.spi_device_flash_all.163025315
97.47 0.01 99.17 0.01 96.19 0.00 98.63 0.00 95.08 0.00 98.04 0.02 95.86 0.00 99.33 0.05 /workspace/coverage/default/47.spi_device_intercept.1073069903
97.48 0.01 99.17 0.00 96.22 0.03 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.38 0.05 /workspace/coverage/default/35.spi_device_intr.2922592655
97.49 0.01 99.17 0.00 96.23 0.01 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.43 0.05 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3748399359
97.50 0.01 99.17 0.00 96.24 0.01 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.48 0.05 /workspace/coverage/default/34.spi_device_fifo_full.163640415
97.51 0.01 99.17 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.52 0.05 /workspace/coverage/default/14.spi_device_stress_all.2026888406
97.51 0.01 99.17 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.57 0.05 /workspace/coverage/default/15.spi_device_fifo_full.1554430986
97.52 0.01 99.17 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.62 0.05 /workspace/coverage/default/16.spi_device_flash_and_tpm.3299938268
97.53 0.01 99.17 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.67 0.05 /workspace/coverage/default/21.spi_device_fifo_underflow_overflow.103052897
97.53 0.01 99.17 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.71 0.05 /workspace/coverage/default/3.spi_device_flash_all.2489960242
97.54 0.01 99.17 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.04 0.00 95.86 0.00 99.76 0.05 /workspace/coverage/default/47.spi_device_flash_all.3075194385
97.55 0.01 99.18 0.01 96.26 0.01 98.63 0.00 95.08 0.00 98.05 0.02 95.86 0.00 99.76 0.00 /workspace/coverage/default/1.spi_device_abort.4099562877
97.55 0.01 99.18 0.00 96.28 0.03 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/11.spi_device_alert_test.1873169361
97.55 0.01 99.18 0.00 96.30 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1172101013
97.55 0.01 99.18 0.00 96.31 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/13.spi_device_rx_async_fifo_reset.615014693
97.56 0.01 99.18 0.00 96.32 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/13.spi_device_tx_async_fifo_reset.462372328
97.56 0.01 99.18 0.00 96.33 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/25.spi_device_flash_and_tpm.1646181632

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3832885057
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1871653731
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3399655165
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2938456869
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3231045631
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3177023029
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4004506159
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.242312807
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1806607576
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2556317597
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2404864284
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4227267646
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4224982287
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1517609934
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.2447091939
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3608217226
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1336588588
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1976553290
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3203741673
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1353688504
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1696041404
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4056864226
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4281673557
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1917335972
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3363403083
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2441212979
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.4164699143
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.946834820
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3813160244
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1495256726
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1117117066
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2608244531
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.4062607953
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3645837983
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4042926965
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3355252645
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4269421121
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4226008201
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.3429027879
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1261427130
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.683892027
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1000417598
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2371090599
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.1611390676
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.578385881
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1491042780
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1064822721
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.413006694
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.506636550
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.3348415962
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2043637271
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3114009848
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1850461298
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1100087182
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.2763599197
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1997119744
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2839534340
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3443746448
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3902124058
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3915586472
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2120597096
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.753716089
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3808823686
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2242887858
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2087841158
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.4078529913
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1962764856
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2567836537
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3548465842
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3428064137
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2949763432
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3448865270
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2686820977
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2162351875
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4064204374
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3144862010
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.414554601
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2993523079
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.769390456
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.961285037
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.4196540451
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3529159262
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3098554013
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.747550558
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1377562448
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.637483456
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.3585772078
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.3045057801
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1171487005
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.2178208950
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.1708177619
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.1575001215
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.3586088916
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.186543754
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.2357370014
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.425953953
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2367766671
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.831308504
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1436845680
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/workspace/coverage/default/8.spi_device_cfg_cmd.1765924766
/workspace/coverage/default/8.spi_device_csb_read.2446991762
/workspace/coverage/default/8.spi_device_dummy_item_extra_dly.1193098318
/workspace/coverage/default/8.spi_device_extreme_fifo_size.3898871917
/workspace/coverage/default/8.spi_device_fifo_full.1311752119
/workspace/coverage/default/8.spi_device_fifo_underflow_overflow.1954556260
/workspace/coverage/default/8.spi_device_flash_all.1214957233
/workspace/coverage/default/8.spi_device_flash_and_tpm.1629170300
/workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3034530274
/workspace/coverage/default/8.spi_device_flash_mode.3616381427
/workspace/coverage/default/8.spi_device_intercept.1797968251
/workspace/coverage/default/8.spi_device_mailbox.3576311227
/workspace/coverage/default/8.spi_device_mem_parity.942368800
/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4021296950
/workspace/coverage/default/8.spi_device_pass_cmd_filtering.2040941008
/workspace/coverage/default/8.spi_device_perf.2626373204
/workspace/coverage/default/8.spi_device_ram_cfg.3989908025
/workspace/coverage/default/8.spi_device_read_buffer_direct.4007737998
/workspace/coverage/default/8.spi_device_rx_async_fifo_reset.735752566
/workspace/coverage/default/8.spi_device_rx_timeout.2652129890
/workspace/coverage/default/8.spi_device_smoke.102960544
/workspace/coverage/default/8.spi_device_stress_all.3991019140
/workspace/coverage/default/8.spi_device_tpm_all.1062819681
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3040274666
/workspace/coverage/default/8.spi_device_tpm_rw.926660678
/workspace/coverage/default/8.spi_device_tpm_sts_read.3463772106
/workspace/coverage/default/8.spi_device_tx_async_fifo_reset.2115425933
/workspace/coverage/default/8.spi_device_txrx.1897222213
/workspace/coverage/default/8.spi_device_upload.2165134095
/workspace/coverage/default/9.spi_device_abort.2049595480
/workspace/coverage/default/9.spi_device_alert_test.1198514249
/workspace/coverage/default/9.spi_device_bit_transfer.3243712143
/workspace/coverage/default/9.spi_device_byte_transfer.2866381854
/workspace/coverage/default/9.spi_device_cfg_cmd.3952349376
/workspace/coverage/default/9.spi_device_csb_read.3382414330
/workspace/coverage/default/9.spi_device_dummy_item_extra_dly.3037721425
/workspace/coverage/default/9.spi_device_extreme_fifo_size.1039127847
/workspace/coverage/default/9.spi_device_fifo_full.3966903217
/workspace/coverage/default/9.spi_device_fifo_underflow_overflow.2364563110
/workspace/coverage/default/9.spi_device_flash_all.2647884211
/workspace/coverage/default/9.spi_device_flash_and_tpm.2892391496
/workspace/coverage/default/9.spi_device_flash_mode.672102577
/workspace/coverage/default/9.spi_device_intercept.3236822861
/workspace/coverage/default/9.spi_device_intr.961526719
/workspace/coverage/default/9.spi_device_mailbox.4180311498
/workspace/coverage/default/9.spi_device_mem_parity.2163968417
/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.326596044
/workspace/coverage/default/9.spi_device_pass_cmd_filtering.407503344
/workspace/coverage/default/9.spi_device_perf.2696755460
/workspace/coverage/default/9.spi_device_ram_cfg.4012694497
/workspace/coverage/default/9.spi_device_read_buffer_direct.1398669295
/workspace/coverage/default/9.spi_device_rx_async_fifo_reset.401653779
/workspace/coverage/default/9.spi_device_rx_timeout.2060224634
/workspace/coverage/default/9.spi_device_smoke.3909743798
/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1840175129
/workspace/coverage/default/9.spi_device_tpm_rw.1370106334
/workspace/coverage/default/9.spi_device_tpm_sts_read.409451107
/workspace/coverage/default/9.spi_device_tx_async_fifo_reset.655848812
/workspace/coverage/default/9.spi_device_txrx.1387968572
/workspace/coverage/default/9.spi_device_upload.1027063382



Total test records in report: 1747
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/44.spi_device_abort.1055920835 Dec 27 01:37:27 PM PST 23 Dec 27 01:37:29 PM PST 23 74513566 ps
T4 /workspace/coverage/default/8.spi_device_ram_cfg.3989908025 Dec 27 01:32:00 PM PST 23 Dec 27 01:32:02 PM PST 23 47413373 ps
T2 /workspace/coverage/default/15.spi_device_extreme_fifo_size.201794949 Dec 27 01:32:02 PM PST 23 Dec 27 01:54:38 PM PST 23 683179931339 ps
T3 /workspace/coverage/default/3.spi_device_mem_parity.3229360489 Dec 27 01:30:21 PM PST 23 Dec 27 01:30:24 PM PST 23 24865688 ps
T5 /workspace/coverage/default/13.spi_device_extreme_fifo_size.3247454764 Dec 27 01:32:28 PM PST 23 Dec 27 01:33:05 PM PST 23 1653201187 ps
T9 /workspace/coverage/default/16.spi_device_stress_all.40532502 Dec 27 01:31:49 PM PST 23 Dec 27 01:50:19 PM PST 23 207338318015 ps
T10 /workspace/coverage/default/16.spi_device_bit_transfer.4270136931 Dec 27 01:32:17 PM PST 23 Dec 27 01:32:35 PM PST 23 1707843038 ps
T16 /workspace/coverage/default/19.spi_device_fifo_full.376094770 Dec 27 01:32:39 PM PST 23 Dec 27 01:39:20 PM PST 23 22249172466 ps
T22 /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2798250079 Dec 27 01:35:46 PM PST 23 Dec 27 01:36:07 PM PST 23 10661440100 ps
T17 /workspace/coverage/default/37.spi_device_upload.1474535311 Dec 27 01:35:52 PM PST 23 Dec 27 01:35:56 PM PST 23 770016088 ps
T18 /workspace/coverage/default/20.spi_device_perf.1286482776 Dec 27 01:32:16 PM PST 23 Dec 27 01:45:07 PM PST 23 70277433232 ps
T19 /workspace/coverage/default/7.spi_device_txrx.3546993780 Dec 27 01:31:13 PM PST 23 Dec 27 01:40:09 PM PST 23 113889172510 ps
T83 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.142279134 Dec 27 12:57:03 PM PST 23 Dec 27 12:57:12 PM PST 23 13060559 ps
T80 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3902124058 Dec 27 12:57:24 PM PST 23 Dec 27 12:57:32 PM PST 23 53888601 ps
T81 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1172101013 Dec 27 12:57:28 PM PST 23 Dec 27 12:57:38 PM PST 23 390265732 ps
T84 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1708177619 Dec 27 12:57:48 PM PST 23 Dec 27 12:57:50 PM PST 23 12720192 ps
T82 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1436845680 Dec 27 12:57:14 PM PST 23 Dec 27 12:57:23 PM PST 23 317884575 ps
T87 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3748399359 Dec 27 12:57:23 PM PST 23 Dec 27 12:57:36 PM PST 23 1172176200 ps
T106 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2073507622 Dec 27 12:57:17 PM PST 23 Dec 27 12:57:39 PM PST 23 571973899 ps
T187 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1997119744 Dec 27 12:57:54 PM PST 23 Dec 27 12:57:59 PM PST 23 61426783 ps
T137 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2686820977 Dec 27 12:57:56 PM PST 23 Dec 27 12:58:00 PM PST 23 295337511 ps
T139 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3136597690 Dec 27 12:57:04 PM PST 23 Dec 27 12:57:37 PM PST 23 10682213511 ps
T171 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2441212979 Dec 27 12:57:13 PM PST 23 Dec 27 12:57:23 PM PST 23 274368912 ps
T85 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3481639661 Dec 27 12:57:26 PM PST 23 Dec 27 12:57:33 PM PST 23 24930650 ps
T86 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3429027879 Dec 27 12:57:13 PM PST 23 Dec 27 12:57:22 PM PST 23 75761482 ps
T140 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3704444543 Dec 27 12:57:22 PM PST 23 Dec 27 12:57:31 PM PST 23 29926517 ps
T172 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3231045631 Dec 27 12:57:07 PM PST 23 Dec 27 12:57:17 PM PST 23 200893335 ps
T173 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3529159262 Dec 27 12:57:05 PM PST 23 Dec 27 12:57:18 PM PST 23 223372622 ps
T174 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1696041404 Dec 27 12:57:13 PM PST 23 Dec 27 12:57:24 PM PST 23 118913104 ps
T175 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.556361116 Dec 27 12:57:14 PM PST 23 Dec 27 12:57:32 PM PST 23 884492979 ps
T141 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.425950560 Dec 27 12:57:22 PM PST 23 Dec 27 12:57:32 PM PST 23 429158425 ps
T163 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4041023876 Dec 27 12:57:21 PM PST 23 Dec 27 12:57:29 PM PST 23 66527929 ps
T164 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1194698692 Dec 27 12:57:15 PM PST 23 Dec 27 12:57:24 PM PST 23 12383953 ps
T142 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3203741673 Dec 27 12:57:08 PM PST 23 Dec 27 12:57:20 PM PST 23 779210415 ps
T165 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1871653731 Dec 27 12:57:10 PM PST 23 Dec 27 12:57:33 PM PST 23 5595467603 ps
T166 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1555059401 Dec 27 12:57:21 PM PST 23 Dec 27 12:57:29 PM PST 23 183550695 ps
T144 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2139210298 Dec 27 12:57:40 PM PST 23 Dec 27 12:57:44 PM PST 23 110543842 ps
T167 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4048290484 Dec 27 12:57:27 PM PST 23 Dec 27 12:57:37 PM PST 23 459054632 ps
T161 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3363403083 Dec 27 12:57:25 PM PST 23 Dec 27 12:57:34 PM PST 23 37426423 ps
T195 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4224982287 Dec 27 12:57:26 PM PST 23 Dec 27 12:57:33 PM PST 23 339341032 ps
T212 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1411668865 Dec 27 12:57:24 PM PST 23 Dec 27 12:57:31 PM PST 23 13902411 ps
T361 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.831308504 Dec 27 12:57:13 PM PST 23 Dec 27 12:57:35 PM PST 23 2784706664 ps
T362 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2120597096 Dec 27 12:57:34 PM PST 23 Dec 27 12:57:40 PM PST 23 254154992 ps
T177 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2792582642 Dec 27 12:57:35 PM PST 23 Dec 27 12:57:41 PM PST 23 27670612 ps
T199 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3448865270 Dec 27 12:57:27 PM PST 23 Dec 27 12:57:35 PM PST 23 50868644 ps
T178 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1891717102 Dec 27 12:57:06 PM PST 23 Dec 27 12:57:17 PM PST 23 106171736 ps
T179 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3120939200 Dec 27 12:57:18 PM PST 23 Dec 27 12:57:28 PM PST 23 254238956 ps
T200 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.425953953 Dec 27 12:57:55 PM PST 23 Dec 27 12:57:57 PM PST 23 47771131 ps
T363 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2404340690 Dec 27 12:57:40 PM PST 23 Dec 27 12:57:43 PM PST 23 11703725 ps
T168 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1806607576 Dec 27 12:57:19 PM PST 23 Dec 27 12:57:48 PM PST 23 3497177527 ps
T180 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2371090599 Dec 27 12:57:23 PM PST 23 Dec 27 12:57:32 PM PST 23 148278824 ps
T176 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1850461298 Dec 27 12:57:26 PM PST 23 Dec 27 12:57:39 PM PST 23 115792712 ps
T364 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3062363752 Dec 27 12:57:58 PM PST 23 Dec 27 12:58:02 PM PST 23 83141159 ps
T201 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1432739704 Dec 27 12:57:27 PM PST 23 Dec 27 12:57:34 PM PST 23 48146306 ps
T365 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1171487005 Dec 27 12:57:34 PM PST 23 Dec 27 12:57:39 PM PST 23 25281816 ps
T366 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3144862010 Dec 27 12:57:15 PM PST 23 Dec 27 12:57:32 PM PST 23 142270383 ps
T196 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.364581258 Dec 27 12:57:09 PM PST 23 Dec 27 12:57:20 PM PST 23 152581731 ps
T367 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.826233878 Dec 27 12:57:23 PM PST 23 Dec 27 12:57:33 PM PST 23 110450005 ps
T169 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4063345375 Dec 27 12:57:23 PM PST 23 Dec 27 12:57:38 PM PST 23 631632981 ps
T181 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2962077982 Dec 27 12:57:19 PM PST 23 Dec 27 12:58:01 PM PST 23 580138874 ps
T197 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1000417598 Dec 27 12:57:25 PM PST 23 Dec 27 12:57:33 PM PST 23 123082251 ps
T170 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3808823686 Dec 27 12:57:25 PM PST 23 Dec 27 12:57:48 PM PST 23 5883305413 ps
T368 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3045057801 Dec 27 12:57:25 PM PST 23 Dec 27 12:57:33 PM PST 23 43656162 ps
T369 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1070499090 Dec 27 12:57:53 PM PST 23 Dec 27 12:57:55 PM PST 23 20436878 ps
T162 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3355252645 Dec 27 12:57:22 PM PST 23 Dec 27 12:57:46 PM PST 23 2346076104 ps
T370 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3870179613 Dec 27 12:57:03 PM PST 23 Dec 27 12:57:12 PM PST 23 49128647 ps
T371 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2448946135 Dec 27 12:57:30 PM PST 23 Dec 27 12:57:36 PM PST 23 17974575 ps
T372 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1784341908 Dec 27 12:57:16 PM PST 23 Dec 27 12:57:39 PM PST 23 2726884325 ps
T182 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2779230763 Dec 27 12:57:26 PM PST 23 Dec 27 12:57:33 PM PST 23 43659645 ps
T373 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.578385881 Dec 27 12:57:26 PM PST 23 Dec 27 12:57:34 PM PST 23 225713080 ps
T374 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3892286923 Dec 27 12:57:18 PM PST 23 Dec 27 12:57:26 PM PST 23 58308504 ps
T145 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4042926965 Dec 27 12:57:16 PM PST 23 Dec 27 12:57:26 PM PST 23 91432979 ps
T146 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2162351875 Dec 27 12:57:26 PM PST 23 Dec 27 12:57:36 PM PST 23 49300555 ps
T147 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1377562448 Dec 27 12:57:26 PM PST 23 Dec 27 12:57:34 PM PST 23 60320322 ps
T375 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1451422364 Dec 27 12:57:21 PM PST 23 Dec 27 12:57:30 PM PST 23 89813404 ps
T376 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1611390676 Dec 27 12:57:12 PM PST 23 Dec 27 12:57:21 PM PST 23 17791025 ps
T377 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4062607953 Dec 27 12:57:11 PM PST 23 Dec 27 12:57:20 PM PST 23 34909183 ps
T378 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1720844574 Dec 27 12:57:48 PM PST 23 Dec 27 12:57:50 PM PST 23 24259110 ps
T379 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.319476336 Dec 27 12:57:07 PM PST 23 Dec 27 12:57:17 PM PST 23 21058873 ps
T380 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4078529913 Dec 27 12:57:40 PM PST 23 Dec 27 12:57:44 PM PST 23 50327698 ps
T381 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2447091939 Dec 27 12:57:12 PM PST 23 Dec 27 12:57:21 PM PST 23 50691618 ps
T382 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2919891741 Dec 27 12:57:28 PM PST 23 Dec 27 12:57:39 PM PST 23 260890570 ps
T383 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2467510147 Dec 27 12:57:34 PM PST 23 Dec 27 12:57:39 PM PST 23 65196129 ps
T198 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1962764856 Dec 27 12:57:26 PM PST 23 Dec 27 12:57:37 PM PST 23 212098661 ps
T384 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4164699143 Dec 27 12:57:31 PM PST 23 Dec 27 12:57:37 PM PST 23 31723616 ps
T202 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2367766671 Dec 27 12:57:16 PM PST 23 Dec 27 12:57:42 PM PST 23 11704283126 ps
T150 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.625252519 Dec 27 12:57:08 PM PST 23 Dec 27 12:57:21 PM PST 23 380624496 ps
T183 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1347581496 Dec 27 12:57:12 PM PST 23 Dec 27 12:57:23 PM PST 23 41178494 ps
T184 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3366181386 Dec 27 12:57:11 PM PST 23 Dec 27 12:57:25 PM PST 23 563827365 ps
T385 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.747550558 Dec 27 12:57:24 PM PST 23 Dec 27 12:57:33 PM PST 23 28320953 ps
T148 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3399655165 Dec 27 12:57:01 PM PST 23 Dec 27 12:57:09 PM PST 23 36793943 ps
T386 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3348415962 Dec 27 12:57:13 PM PST 23 Dec 27 12:57:22 PM PST 23 25433056 ps
T387 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3563612987 Dec 27 12:57:28 PM PST 23 Dec 27 12:57:36 PM PST 23 43704673 ps
T388 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3586088916 Dec 27 12:57:28 PM PST 23 Dec 27 12:57:36 PM PST 23 37771385 ps
T151 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2323949106 Dec 27 12:57:28 PM PST 23 Dec 27 12:57:40 PM PST 23 272633977 ps
T389 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3813160244 Dec 27 12:57:52 PM PST 23 Dec 27 12:57:57 PM PST 23 270461771 ps
T390 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2608244531 Dec 27 12:57:27 PM PST 23 Dec 27 12:57:35 PM PST 23 162925867 ps
T221 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1321041276 Dec 27 12:57:09 PM PST 23 Dec 27 12:57:36 PM PST 23 625629001 ps
T391 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2219686606 Dec 27 12:57:04 PM PST 23 Dec 27 12:57:15 PM PST 23 117909700 ps
T392 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1064822721 Dec 27 12:57:23 PM PST 23 Dec 27 12:57:37 PM PST 23 285378943 ps
T393 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.755343998 Dec 27 12:57:46 PM PST 23 Dec 27 12:57:48 PM PST 23 37294377 ps
T394 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4004506159 Dec 27 12:57:18 PM PST 23 Dec 27 12:57:39 PM PST 23 466255188 ps
T185 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3979670464 Dec 27 12:57:11 PM PST 23 Dec 27 12:57:38 PM PST 23 736362845 ps
T395 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2142704084 Dec 27 12:57:15 PM PST 23 Dec 27 12:57:24 PM PST 23 18379131 ps
T396 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.753716089 Dec 27 12:57:28 PM PST 23 Dec 27 12:57:37 PM PST 23 75442981 ps
T397 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1117117066 Dec 27 12:57:29 PM PST 23 Dec 27 12:57:36 PM PST 23 24421699 ps
T398 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2567836537 Dec 27 12:57:34 PM PST 23 Dec 27 12:57:45 PM PST 23 204960150 ps
T399 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.754594291 Dec 27 12:57:16 PM PST 23 Dec 27 12:57:28 PM PST 23 155904385 ps
T186 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4007591879 Dec 27 12:57:19 PM PST 23 Dec 27 12:57:28 PM PST 23 19538151 ps
T400 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2949763432 Dec 27 12:57:40 PM PST 23 Dec 27 12:57:45 PM PST 23 31083693 ps
T401 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4037799518 Dec 27 12:57:49 PM PST 23 Dec 27 12:57:51 PM PST 23 36157639 ps
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