Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

Group : spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	16	0	16	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_bit_order	2	0	2	100.00	100	1	1	2
cp_cpha	2	0	2	100.00	100	1	1	2
cp_cpol	2	0	2	100.00	100	1	1	2
cp_rx_order	2	0	2	100.00	100	1	1	2
rx_order	2	0	2	100.00	100	1	1	2
tx_order	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_bit_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bit_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2740917

1

T2

3718

T5

633

T9

25387

auto[1]

3005325

1

T5

772

T9

18182

T10

36

---

Summary for Variable cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpha

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3139000

1

T9

24372

T10

58

T18

3695

auto[1]

2607242

1

T2

3718

T5

1405

T9

19197

---

Summary for Variable cp_cpol

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpol

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2879414

1

T5

633

T9

23076

T10

43

auto[1]

2866828

1

T2

3718

T5

772

T9

20493

---

Summary for Variable cp_rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2943031

1

T2

3718

T9

20493

T10

30

auto[1]

2803211

1

T5

1405

T9

23076

T10

50

---

Summary for Variable rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2943031

1

T2

3718

T9

20493

T10

30

auto[1]

2803211

1

T5

1405

T9

23076

T10

50

---

Summary for Variable tx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for tx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2740917

1

T2

3718

T5

633

T9

25387

auto[1]

3005325

1

T5

772

T9

18182

T10

36

---

Summary for Cross cr_all

Samples crossed: tx_order rx_order cp_cpol cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

tx_order

rx_order

cp_cpol

cp_cpha

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

354732

1

T10

5

T19

1597

T21

7587

auto[0]

auto[0]

auto[0]

auto[1]

304078

1

T10

5

T19

6945

T21

9679

auto[0]

auto[0]

auto[1]

auto[0]

322445

1

T9

6190

T10

1

T73

2249

auto[0]

auto[0]

auto[1]

auto[1]

336794

1

T2

3718

T9

14303

T10

3

auto[0]

auto[1]

auto[0]

auto[0]

402198

1

T10

8

T18

3695

T73

2919

auto[0]

auto[1]

auto[0]

auto[1]

271760

1

T5

633

T9

4894

T48

2154

auto[0]

auto[1]

auto[1]

auto[0]

328259

1

T10

22

T66

1027

T55

3

auto[0]

auto[1]

auto[1]

auto[1]

420651

1

T75

3016

T6

7128

T64

253

auto[1]

auto[0]

auto[0]

auto[0]

430291

1

T10

5

T21

6997

T48

2996

auto[1]

auto[0]

auto[0]

auto[1]

383159

1

T10

7

T16

5314

T125

2

auto[1]

auto[0]

auto[1]

auto[0]

466507

1

T10

4

T19

4304

T56

1

auto[1]

auto[0]

auto[1]

auto[1]

345025

1

T52

5373

T224

3033

T125

8

auto[1]

auto[1]

auto[0]

auto[0]

459401

1

T9

18182

T10

9

T53

4463

auto[1]

auto[1]

auto[0]

auto[1]

273795

1

T10

4

T18

9233

T125

5

auto[1]

auto[1]

auto[1]

auto[0]

375167

1

T10

4

T20

117

T48

2716

auto[1]

auto[1]

auto[1]

auto[1]

271980

1

T5

772

T10

3

T75

3022