Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33306	1			T17	12		T23	10		T11	6
auto[SpiFlashAddrCfg]	7532	1			T11	8		T13	4		T6	22
auto[SpiFlashAddr3b]	8960	1			T23	2		T11	4		T12	4
auto[SpiFlashAddr4b]	7652	1			T11	2		T12	2		T13	8

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33069

1

T17

12

T23

12

T13

17

auto[1]

24381

1

T11

20

T12

8

T6

87

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29938

1

T17

2

T23

2

T11

16

auto[1]

27512

1

T17

10

T23

10

T11

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37941	1			T17	12		T23	10		T11	8
values[1]	989	1			T6	8		T7	1		T8	8
values[2]	1496	1			T6	5		T7	5		T8	17
values[3]	1513	1			T11	4		T6	4		T7	7
values[4]	1387	1			T6	1		T8	6		T24	1
values[5]	1408	1			T11	2		T6	5		T7	4
values[6]	1430	1			T13	4		T6	4		T7	9
values[7]	1432	1			T6	6		T7	4		T8	13
values[8]	9854	1			T23	2		T11	6		T12	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29228

1

T17

12

T23

12

T11

20

auto[1]

28222

1

T13

17

T6

141

T7

303

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55310

1

T17

12

T23

12

T11

20

write

2140

1

T6

7

T7

9

T8

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19536

1

T17

2

T11

8

T12

6

valids[0x1]

37914

1

T17

10

T23

12

T11

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1542	1			T17	6		T23	2		T11	4
internal_process_ops[0x5a]	1506	1			T23	2		T11	2		T6	4
internal_process_ops[0x05]	19769	1			T6	46		T7	208		T8	163
internal_process_ops[0x35]	1559	1			T17	2		T23	6		T6	2
internal_process_ops[0x15]	1596	1			T23	2		T11	2		T6	9
internal_process_ops[0x03]	1079	1			T13	5		T6	1		T7	1
internal_process_ops[0x0b]	1096	1			T13	3		T6	4		T7	1
internal_process_ops[0x3b]	1000	1			T12	2		T6	2		T8	9
internal_process_ops[0x6b]	1100	1			T6	3		T7	2		T8	10
internal_process_ops[0xbb]	1216	1			T11	2		T13	5		T6	2
internal_process_ops[0xeb]	1059	1			T13	4		T14	6		T6	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56377

1

T17

12

T23

12

T11

20

auto[1]

1073

1

T6

4

T7

7

T8

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55420

1

T17

12

T23

12

T11

20

auto[1]

2030

1

T6

10

T7

13

T8

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9974

1

T17

12

T23

10

T26

18

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6298

1

T11

6

T12

2

T6

1

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2028

1

T6

1

T8

24

T24

3

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1748

1

T11

8

T6

2

T8

20

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2455

1

T23

2

T14

6

T6

1

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1908

1

T11

4

T12

4

T6

1

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2079

1

T6

5

T33

6

T8

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1766

1

T11

2

T12

2

T6

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

82

1

T8

2

T213

2

T214

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

50

1

T28

1

T30

2

T36

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

54

1

T28

3

T30

6

T36

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

70

1

T8

2

T28

1

T38

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

95

1

T25

4

T215

4

T36

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

42

1

T28

1

T38

3

T39

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

40

1

T28

1

T30

1

T38

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

64

1

T27

4

T28

2

T37

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

57

1

T8

1

T28

1

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

45

1

T76

2

T216

2

T77

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

54

1

T28

1

T36

1

T39

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

83

1

T30

4

T38

3

T40

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

60

1

T24

3

T217

4

T38

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

72

1

T8

1

T28

1

T40

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

33

1

T28

1

T30

1

T40

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

71

1

T28

1

T31

1

T35

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9919

1

T6

39

T7

134

T50

152

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6577

1

T6

47

T7

115

T50

94

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1723

1

T13

4

T6

6

T7

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1487

1

T6

11

T7

10

T50

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2076

1

T13

5

T6

8

T7

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2002

1

T6

12

T7

12

T50

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1762

1

T13

8

T6

6

T7

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1508

1

T6

5

T7

9

T50

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

80

1

T7

2

T50

1

T61

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

58

1

T6

1

T61

1

T63

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

73

1

T50

1

T61

3

T63

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

71

1

T6

1

T61

1

T63

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

65

1

T61

2

T131

1

T76

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

88

1

T6

1

T7

1

T60

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

75

1

T131

1

T218

3

T152

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

77

1

T6

1

T7

3

T50

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

62

1

T6

1

T61

1

T76

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

63

1

T131

1

T219

1

T76

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

89

1

T6

1

T62

2

T63

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

66

1

T7

1

T61

1

T63

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

60

1

T50

3

T61

3

T63

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

74

1

T7

2

T60

4

T61

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

88

1

T6

1

T61

2

T63

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

79

1

T61

2

T62

1

T131

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3912	1			T17	2		T26	18		T29	26
auto[0]	values[0]	valids[0x1]	14955	1			T17	10		T23	10		T11	8
auto[0]	values[1]	valids[0x1]	518	1			T6	2		T8	8		T24	1
auto[0]	values[2]	valids[0x0]	578	1			T6	2		T8	13		T32	2
auto[0]	values[2]	valids[0x1]	256	1			T8	4		T32	2		T28	1
auto[0]	values[3]	valids[0x0]	510	1			T11	4		T6	2		T8	1
auto[0]	values[3]	valids[0x1]	288	1			T6	2		T8	2		T24	1
auto[0]	values[4]	valids[0x0]	487	1			T8	6		T32	2		T220	2
auto[0]	values[4]	valids[0x1]	264	1			T24	1		T28	2		T30	3
auto[0]	values[5]	valids[0x0]	485	1			T11	2		T6	2		T8	3
auto[0]	values[5]	valids[0x1]	290	1			T8	4		T34	2		T28	6
auto[0]	values[6]	valids[0x0]	480	1			T8	5		T24	2		T34	2
auto[0]	values[6]	valids[0x1]	259	1			T8	3		T25	2		T28	3
auto[0]	values[7]	valids[0x0]	483	1			T8	7		T25	8		T28	10
auto[0]	values[7]	valids[0x1]	266	1			T8	6		T24	2		T28	3
auto[0]	values[8]	valids[0x0]	3254	1			T11	2		T12	6		T14	6
auto[0]	values[8]	valids[0x1]	1943	1			T23	2		T11	4		T12	2
auto[1]	values[0]	valids[0x0]	4129	1			T6	17		T7	20		T50	15
auto[1]	values[0]	valids[0x1]	14945	1			T6	77		T7	236		T50	241
auto[1]	values[1]	valids[0x1]	471	1			T6	6		T7	1		T50	2
auto[1]	values[2]	valids[0x0]	419	1			T7	3		T50	1		T60	1
auto[1]	values[2]	valids[0x1]	243	1			T6	3		T7	2		T51	2
auto[1]	values[3]	valids[0x0]	420	1			T7	1		T44	4		T50	1
auto[1]	values[3]	valids[0x1]	295	1			T7	6		T61	3		T63	10
auto[1]	values[4]	valids[0x0]	383	1			T50	1		T60	6		T61	13
auto[1]	values[4]	valids[0x1]	253	1			T6	1		T60	2		T61	4
auto[1]	values[5]	valids[0x0]	374	1			T6	1		T7	4		T61	12
auto[1]	values[5]	valids[0x1]	259	1			T6	2		T61	5		T62	1
auto[1]	values[6]	valids[0x0]	388	1			T13	4		T6	1		T7	5
auto[1]	values[6]	valids[0x1]	303	1			T6	3		T7	4		T51	6
auto[1]	values[7]	valids[0x0]	408	1			T6	2		T7	1		T50	2
auto[1]	values[7]	valids[0x1]	275	1			T6	4		T7	3		T50	3
auto[1]	values[8]	valids[0x0]	2826	1			T13	5		T6	10		T7	9
auto[1]	values[8]	valids[0x1]	1831	1			T13	8		T6	14		T7	8