Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18262

1

T17

3

T23

17

T11

1

auto[1]

18169

1

T6

41

T7

203

T8

157

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13797

1

T17

1

T23

17

T11

1

auto[1]

22634

1

T17

2

T6

57

T7

217

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	6591	1			T17	3		T23	2		T11	1
auto[524288:1048575]	4537	1			T23	3		T13	2		T14	1
auto[1048576:1572863]	4210	1			T23	3		T13	3		T26	3
auto[1572864:2097151]	4211	1			T13	6		T14	1		T26	1
auto[2097152:2621439]	4261	1			T23	4		T26	2		T29	4
auto[2621440:3145727]	3981	1			T23	1		T26	2		T29	3
auto[3145728:3670015]	4665	1			T23	2		T14	1		T6	1
auto[3670016:4194303]	3975	1			T23	2		T13	3		T26	6

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35845

1

T17

3

T23

17

T11

1

auto[1]

586

1

T6

7

T7

14

T8

4

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19779

1

T17

3

T23

9

T11

1

auto[1]

16652

1

T23

8

T13

10

T14

2

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1351	1			T17	1		T11	1		T12	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	708	1			T17	2		T6	9		T7	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	731	1			T13	2		T26	2		T7	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	391	1			T7	3		T8	2		T60	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	640	1			T23	3		T6	1		T7	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	388	1			T7	2		T8	2		T61	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	675	1			T13	4		T26	1		T29	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	374	1			T7	6		T8	6		T61	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	712	1			T23	3		T26	2		T29	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	376	1			T6	2		T50	7		T61	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	705	1			T23	1		T26	2		T29	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	387	1			T8	2		T61	5		T30	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	752	1			T14	1		T6	1		T7	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	418	1			T7	4		T8	2		T61	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	631	1			T23	2		T26	6		T29	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	338	1			T6	1		T7	3		T8	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	681	1			T23	2		T13	2		T26	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	373	1			T8	1		T24	1		T50	3
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	707	1			T23	3		T14	1		T29	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	387	1			T7	1		T8	1		T60	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	671	1			T13	3		T26	3		T6	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	420	1			T8	3		T24	2		T50	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	691	1			T13	2		T14	1		T29	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	416	1			T6	2		T7	1		T50	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	674	1			T23	1		T29	3		T6	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	364	1			T6	4		T7	4		T8	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	710	1			T6	10		T7	3		T24	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	421	1			T6	7		T7	1		T8	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	731	1			T23	2		T8	8		T275	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	364	1			T8	2		T50	2		T61	7
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	705	1			T13	3		T6	1		T7	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	370	1			T6	1		T8	2		T50	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	241	1			T6	4		T7	1		T8	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2092	1			T6	6		T7	13		T8	42
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	126	1			T7	1		T8	1		T60	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1313	1			T7	34		T8	47		T60	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	120	1			T7	2		T61	1		T63	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	939	1			T7	32		T61	5		T63	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	114	1			T7	3		T63	1		T38	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	939	1			T7	28		T63	2		T38	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	126	1			T50	4		T63	1		T28	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1243	1			T50	107		T63	2		T28	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	109	1			T131	2		T219	2		T76	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	673	1			T131	5		T219	8		T76	29
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	143	1			T7	1		T61	3		T63	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1131	1			T7	9		T61	11		T63	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	103	1			T7	2		T8	1		T61	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	790	1			T7	27		T8	7		T61	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	119	1			T50	1		T60	2		T61	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	1026	1			T50	36		T60	22		T61	24
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	113	1			T7	1		T60	1		T61	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	769	1			T7	4		T60	3		T61	14
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	130	1			T8	2		T63	2		T131	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	902	1			T8	22		T63	4		T131	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	118	1			T50	1		T60	1		T61	5
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	884	1			T50	37		T60	2		T61	27
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	101	1			T6	1		T7	2		T8	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	665	1			T6	3		T7	43		T8	8
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	130	1			T6	4		T50	1		T60	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	846	1			T6	18		T50	24		T60	58
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	128	1			T8	2		T61	2		T63	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	998	1			T8	7		T61	30		T63	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	109	1			T6	1		T8	1		T60	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	929	1			T6	4		T8	14		T60	10

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	9489	1			T17	3		T23	9		T11	1
auto[0]	auto[0]	auto[1]	88	1			T7	3		T60	1		T61	1
auto[0]	auto[1]	auto[0]	8600	1			T23	8		T13	10		T14	2
auto[0]	auto[1]	auto[1]	85	1			T6	1		T7	1		T8	1
auto[1]	auto[0]	auto[0]	9987	1			T6	10		T7	145		T8	99
auto[1]	auto[0]	auto[1]	215	1			T7	8		T8	1		T60	1
auto[1]	auto[1]	auto[0]	7769	1			T6	25		T7	48		T8	55
auto[1]	auto[1]	auto[1]	198	1			T6	6		T7	2		T8	2