Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_rx_size	8	1	7	87.50	100	1	1	0

Summary for Variable cp_rx_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for cp_rx_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
specific_sizes[4092]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
specific_sizes[4]	54599	1			T2	3718		T99	3		T204	2807
specific_sizes[2048]	3	1			T205	1		T206	2		-	-
sizes[0]	71743	1			T2	3718		T21	260		T53	99
sizes[1]	4743	1			T9	228		T48	52		T54	49
sizes[2]	2003	1			T5	1		T67	123		T75	37
sizes[3]	294	1			T207	33		T208	43		T209	97
sizes[4]	177	1			T88	65		T210	65		T211	12