Group : spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg
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Group : spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv



Summary for Group spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_tx_size 8 0 8 100.00 100 1 1 0


Summary for Variable cp_tx_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_tx_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
specific_sizes[4] 35306 1 T66 1683 T49 1221 T114 1334
specific_sizes[2048] 6357 1 T2 1706 T89 178 T276 63
specific_sizes[4092] 2259 1 T89 131 T277 411 T278 348
sizes[0] 586065 1 T19 417 T21 602 T66 1683
sizes[1] 355521 1 T9 1416 T16 9981 T18 12419
sizes[2] 187820 1 T2 1706 T67 5 T52 9913
sizes[3] 35975 1 T279 9525 T280 605 T281 772
sizes[4] 3929 1 T282 1181 T89 131 T277 411

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%