Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17039

1

T17

12

T23

12

T14

6

auto[1]

12189

1

T11

20

T12

8

T6

8

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4013	1			T8	200		T28	102		T30	84
values[1]	3472	1			T14	6		T24	20		T45	2
values[2]	3866	1			T11	20		T6	20		T32	18
values[3]	3258	1			T17	12		T23	12		T8	97
values[4]	3954	1			T29	26		T33	6		T8	40
values[5]	3159	1			T283	4		T28	49		T30	65
values[6]	3621	1			T12	8		T26	18		T24	20
values[7]	3885	1			T8	20		T34	6		T25	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3659	1			T8	40		T24	20		T45	2
values[1]	4125	1			T14	6		T6	20		T33	6
values[2]	3045	1			T17	12		T26	18		T8	20
values[3]	3439	1			T12	8		T8	132		T25	22
values[4]	3660	1			T8	20		T24	20		T28	64
values[5]	3521	1			T28	134		T30	32		T284	4
values[6]	3499	1			T23	12		T29	26		T8	37
values[7]	4280	1			T11	20		T32	18		T275	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	469	1			T28	7		T30	9		T236	12
auto[0]	values[0]	values[1]	354	1			T8	27		T28	10		T36	16
auto[0]	values[0]	values[2]	129	1			T77	12		T79	13		T267	20
auto[0]	values[0]	values[3]	170	1			T8	13		T38	7		T39	10
auto[0]	values[0]	values[4]	294	1			T36	11		T235	15		T132	24
auto[0]	values[0]	values[5]	399	1			T28	22		T285	12		T77	10
auto[0]	values[0]	values[6]	320	1			T28	20		T264	26		T36	13
auto[0]	values[0]	values[7]	176	1			T30	13		T239	8		T132	10
auto[0]	values[1]	values[0]	255	1			T24	13		T45	2		T227	37
auto[0]	values[1]	values[1]	176	1			T14	6		T30	15		T36	8
auto[0]	values[1]	values[2]	171	1			T234	12		T227	30		T286	11
auto[0]	values[1]	values[3]	191	1			T220	4		T30	10		T76	11
auto[0]	values[1]	values[4]	240	1			T30	15		T260	18		T76	10
auto[0]	values[1]	values[5]	244	1			T77	12		T227	53		T287	28
auto[0]	values[1]	values[6]	183	1			T30	6		T77	57		T246	31
auto[0]	values[1]	values[7]	516	1			T30	19		T288	12		T231	10
auto[0]	values[2]	values[0]	263	1			T213	8		T245	12		T289	13
auto[0]	values[2]	values[1]	329	1			T6	12		T79	9		T227	10
auto[0]	values[2]	values[2]	397	1			T38	12		T40	10		T290	18
auto[0]	values[2]	values[3]	246	1			T28	21		T30	14		T38	7
auto[0]	values[2]	values[4]	223	1			T28	7		T31	6		T291	18
auto[0]	values[2]	values[5]	233	1			T28	12		T274	4		T261	16
auto[0]	values[2]	values[6]	215	1			T30	14		T292	24		T36	16
auto[0]	values[2]	values[7]	262	1			T32	18		T39	10		T234	20
auto[0]	values[3]	values[0]	290	1			T8	13		T76	15		T38	12
auto[0]	values[3]	values[1]	317	1			T30	9		T39	15		T293	10
auto[0]	values[3]	values[2]	151	1			T17	12		T8	11		T30	14
auto[0]	values[3]	values[3]	209	1			T38	8		T77	24		T294	17
auto[0]	values[3]	values[4]	278	1			T8	10		T28	24		T295	16
auto[0]	values[3]	values[5]	142	1			T28	9		T296	6		T237	16
auto[0]	values[3]	values[6]	196	1			T23	12		T8	10		T30	12
auto[0]	values[3]	values[7]	334	1			T275	2		T297	26		T39	11
auto[0]	values[4]	values[0]	242	1			T8	11		T40	9		T77	13
auto[0]	values[4]	values[1]	344	1			T33	6		T8	13		T229	14
auto[0]	values[4]	values[2]	342	1			T28	13		T40	38		T231	12
auto[0]	values[4]	values[3]	377	1			T30	12		T38	11		T241	71
auto[0]	values[4]	values[4]	168	1			T234	37		T286	9		T242	13
auto[0]	values[4]	values[5]	274	1			T28	7		T30	13		T298	6
auto[0]	values[4]	values[6]	310	1			T29	26		T76	10		T299	26
auto[0]	values[4]	values[7]	308	1			T143	8		T76	11		T40	14
auto[0]	values[5]	values[0]	309	1			T30	15		T216	14		T234	13
auto[0]	values[5]	values[1]	185	1			T283	4		T252	10		T247	7
auto[0]	values[5]	values[2]	169	1			T30	14		T38	13		T214	38
auto[0]	values[5]	values[3]	132	1			T40	10		T79	11		T231	10
auto[0]	values[5]	values[4]	189	1			T39	7		T77	13		T300	8
auto[0]	values[5]	values[5]	192	1			T28	22		T38	15		T39	21
auto[0]	values[5]	values[6]	132	1			T234	62		T227	8		T132	15
auto[0]	values[5]	values[7]	433	1			T28	13		T30	14		T301	67
auto[0]	values[6]	values[0]	266	1			T302	6		T253	9		T242	15
auto[0]	values[6]	values[1]	411	1			T38	9		T259	28		T303	10
auto[0]	values[6]	values[2]	206	1			T26	18		T250	16		T77	8
auto[0]	values[6]	values[3]	154	1			T30	11		T231	11		T304	8
auto[0]	values[6]	values[4]	283	1			T24	16		T39	26		T79	12
auto[0]	values[6]	values[5]	209	1			T284	4		T39	11		T263	10
auto[0]	values[6]	values[6]	441	1			T240	18		T40	14		T234	53
auto[0]	values[6]	values[7]	217	1			T215	34		T38	12		T40	9
auto[0]	values[7]	values[0]	242	1			T256	18		T305	11		T79	34
auto[0]	values[7]	values[1]	303	1			T39	12		T154	11		T231	28
auto[0]	values[7]	values[2]	297	1			T217	10		T154	16		T231	25
auto[0]	values[7]	values[3]	410	1			T8	8		T25	22		T306	14
auto[0]	values[7]	values[4]	313	1			T30	13		T36	16		T38	15
auto[0]	values[7]	values[5]	179	1			T38	11		T39	9		T40	12
auto[0]	values[7]	values[6]	322	1			T34	6		T38	9		T234	46
auto[0]	values[7]	values[7]	308	1			T39	11		T40	13		T234	10
auto[1]	values[0]	values[0]	247	1			T28	18		T30	40		T39	12
auto[1]	values[0]	values[1]	270	1			T8	61		T28	10		T36	4
auto[1]	values[0]	values[2]	127	1			T77	8		T79	7		T267	10
auto[1]	values[0]	values[3]	262	1			T8	99		T38	30		T39	10
auto[1]	values[0]	values[4]	166	1			T36	21		T235	9		T132	23
auto[1]	values[0]	values[5]	261	1			T28	9		T77	10		T231	25
auto[1]	values[0]	values[6]	243	1			T28	6		T36	11		T225	6
auto[1]	values[0]	values[7]	126	1			T30	22		T269	10		T132	30
auto[1]	values[1]	values[0]	149	1			T24	7		T227	9		T237	12
auto[1]	values[1]	values[1]	199	1			T30	5		T36	15		T38	7
auto[1]	values[1]	values[2]	186	1			T234	24		T227	7		T286	9
auto[1]	values[1]	values[3]	234	1			T30	10		T76	9		T237	6
auto[1]	values[1]	values[4]	122	1			T30	5		T76	10		T40	10
auto[1]	values[1]	values[5]	214	1			T77	18		T227	10		T132	19
auto[1]	values[1]	values[6]	78	1			T30	14		T77	13		T246	9
auto[1]	values[1]	values[7]	314	1			T30	21		T231	10		T247	16
auto[1]	values[2]	values[0]	141	1			T245	18		T289	17		T255	6
auto[1]	values[2]	values[1]	312	1			T6	8		T270	24		T37	36
auto[1]	values[2]	values[2]	219	1			T27	18		T38	8		T40	10
auto[1]	values[2]	values[3]	208	1			T28	10		T30	34		T38	13
auto[1]	values[2]	values[4]	229	1			T28	26		T31	14		T231	8
auto[1]	values[2]	values[5]	161	1			T28	16		T38	11		T294	7
auto[1]	values[2]	values[6]	210	1			T30	6		T36	4		T38	5
auto[1]	values[2]	values[7]	218	1			T11	20		T39	10		T234	12
auto[1]	values[3]	values[0]	179	1			T8	7		T76	5		T38	23
auto[1]	values[3]	values[1]	97	1			T30	11		T39	5		T237	8
auto[1]	values[3]	values[2]	67	1			T8	9		T30	8		T247	11
auto[1]	values[3]	values[3]	116	1			T38	12		T307	4		T77	49
auto[1]	values[3]	values[4]	175	1			T8	10		T28	7		T231	6
auto[1]	values[3]	values[5]	256	1			T28	11		T237	11		T247	38
auto[1]	values[3]	values[6]	203	1			T8	27		T30	8		T31	8
auto[1]	values[3]	values[7]	248	1			T39	9		T154	6		T234	11
auto[1]	values[4]	values[0]	131	1			T8	9		T40	11		T77	21
auto[1]	values[4]	values[1]	242	1			T8	7		T40	3		T234	65
auto[1]	values[4]	values[2]	145	1			T28	12		T40	28		T231	15
auto[1]	values[4]	values[3]	300	1			T30	8		T38	9		T40	32
auto[1]	values[4]	values[4]	170	1			T234	8		T286	11		T242	14
auto[1]	values[4]	values[5]	198	1			T28	19		T30	19		T305	10
auto[1]	values[4]	values[6]	261	1			T76	23		T40	13		T77	11
auto[1]	values[4]	values[7]	142	1			T76	9		T40	13		T245	6
auto[1]	values[5]	values[0]	177	1			T30	5		T216	6		T234	7
auto[1]	values[5]	values[1]	148	1			T247	13		T243	10		T267	5
auto[1]	values[5]	values[2]	193	1			T30	11		T38	7		T267	12
auto[1]	values[5]	values[3]	137	1			T40	10		T79	45		T231	10
auto[1]	values[5]	values[4]	241	1			T39	18		T77	46		T237	27
auto[1]	values[5]	values[5]	266	1			T28	7		T38	5		T39	11
auto[1]	values[5]	values[6]	77	1			T234	9		T227	12		T132	5
auto[1]	values[5]	values[7]	179	1			T28	7		T30	6		T38	10
auto[1]	values[6]	values[0]	166	1			T253	11		T242	5		T308	10
auto[1]	values[6]	values[1]	257	1			T38	49		T235	8		T247	11
auto[1]	values[6]	values[2]	114	1			T77	18		T245	23		T246	9
auto[1]	values[6]	values[3]	87	1			T12	8		T30	9		T231	9
auto[1]	values[6]	values[4]	330	1			T24	4		T39	6		T79	8
auto[1]	values[6]	values[5]	120	1			T39	9		T263	13		T234	5
auto[1]	values[6]	values[6]	126	1			T40	6		T234	9		T227	23
auto[1]	values[6]	values[7]	234	1			T38	8		T40	17		T77	14
auto[1]	values[7]	values[0]	133	1			T305	9		T79	8		T253	11
auto[1]	values[7]	values[1]	181	1			T39	8		T154	9		T231	18
auto[1]	values[7]	values[2]	132	1			T35	22		T154	4		T231	27
auto[1]	values[7]	values[3]	206	1			T8	12		T77	8		T234	14
auto[1]	values[7]	values[4]	239	1			T30	41		T36	4		T38	5
auto[1]	values[7]	values[5]	173	1			T38	53		T39	11		T40	12
auto[1]	values[7]	values[6]	182	1			T38	48		T234	5		T237	13
auto[1]	values[7]	values[7]	265	1			T39	9		T40	7		T234	10