Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	12	0	12	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6539028	1			T1	2		T4	1		T2	2
all_pins[1]	6539028	1			T1	2		T4	1		T2	2
all_pins[2]	6539028	1			T1	2		T4	1		T2	2
all_pins[3]	6539028	1			T1	2		T4	1		T2	2
all_pins[4]	6539028	1			T1	2		T4	1		T2	2
all_pins[5]	6539028	1			T1	2		T4	1		T2	2
all_pins[6]	6539028	1			T1	2		T4	1		T2	2
all_pins[7]	6539028	1			T1	2		T4	1		T2	2
all_pins[8]	6539028	1			T1	2		T4	1		T2	2
all_pins[9]	6539028	1			T1	2		T4	1		T2	2
all_pins[10]	6539028	1			T1	2		T4	1		T2	2
all_pins[11]	6539028	1			T1	2		T4	1		T2	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	78299011	1			T1	24		T4	12		T2	23
values[0x1]	169325	1			T2	1		T9	6		T16	1
transitions[0x0=>0x1]	168488	1			T2	1		T9	3		T16	1
transitions[0x1=>0x0]	168506	1			T2	1		T9	3		T16	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6538473	1			T1	2		T4	1		T2	1
all_pins[0]	values[0x1]	555	1			T2	1		T9	1		T83	4
all_pins[0]	transitions[0x0=>0x1]	325	1			T2	1		T83	1		T85	1
all_pins[0]	transitions[0x1=>0x0]	157726	1			T9	1		T83	1		T84	1
all_pins[1]	values[0x0]	6381072	1			T1	2		T4	1		T2	2
all_pins[1]	values[0x1]	157956	1			T9	2		T83	4		T84	1
all_pins[1]	transitions[0x0=>0x1]	157827	1			T9	1		T83	2		T85	3
all_pins[1]	transitions[0x1=>0x0]	452	1			T16	1		T19	1		T85	5
all_pins[2]	values[0x0]	6538447	1			T1	2		T4	1		T2	2
all_pins[2]	values[0x1]	581	1			T9	1		T16	1		T19	1
all_pins[2]	transitions[0x0=>0x1]	542	1			T9	1		T16	1		T19	1
all_pins[2]	transitions[0x1=>0x0]	86	1			T83	3		T84	1		T85	1
all_pins[3]	values[0x0]	6538903	1			T1	2		T4	1		T2	2
all_pins[3]	values[0x1]	125	1			T83	4		T84	1		T85	1
all_pins[3]	transitions[0x0=>0x1]	92	1			T83	4		T84	1		T85	1
all_pins[3]	transitions[0x1=>0x0]	441	1			T9	1		T83	1		T85	6
all_pins[4]	values[0x0]	6538554	1			T1	2		T4	1		T2	2
all_pins[4]	values[0x1]	474	1			T9	1		T83	1		T85	6
all_pins[4]	transitions[0x0=>0x1]	278	1			T83	1		T85	5		T86	3
all_pins[4]	transitions[0x1=>0x0]	1814	1			T83	3		T84	1		T85	1
all_pins[5]	values[0x0]	6537018	1			T1	2		T4	1		T2	2
all_pins[5]	values[0x1]	2010	1			T9	1		T83	3		T84	1
all_pins[5]	transitions[0x0=>0x1]	1977	1			T9	1		T83	3		T84	1
all_pins[5]	transitions[0x1=>0x0]	693	1			T85	2		T86	1		T212	2
all_pins[6]	values[0x0]	6538302	1			T1	2		T4	1		T2	2
all_pins[6]	values[0x1]	726	1			T85	3		T86	1		T212	3
all_pins[6]	transitions[0x0=>0x1]	688	1			T85	1		T86	1		T212	3
all_pins[6]	transitions[0x1=>0x0]	226	1			T83	3		T84	1		T85	4
all_pins[7]	values[0x0]	6538764	1			T1	2		T4	1		T2	2
all_pins[7]	values[0x1]	264	1			T83	3		T84	1		T85	6
all_pins[7]	transitions[0x0=>0x1]	241	1			T83	3		T84	1		T85	4
all_pins[7]	transitions[0x1=>0x0]	91	1			T83	1		T85	1		T86	1
all_pins[8]	values[0x0]	6538914	1			T1	2		T4	1		T2	2
all_pins[8]	values[0x1]	114	1			T83	1		T85	3		T86	3
all_pins[8]	transitions[0x0=>0x1]	88	1			T83	1		T85	2		T86	2
all_pins[8]	transitions[0x1=>0x0]	79	1			T83	5		T85	3		T199	2
all_pins[9]	values[0x0]	6538923	1			T1	2		T4	1		T2	2
all_pins[9]	values[0x1]	105	1			T83	5		T85	4		T86	1
all_pins[9]	transitions[0x0=>0x1]	73	1			T83	3		T85	2		T86	1
all_pins[9]	transitions[0x1=>0x0]	68	1			T84	1		T86	1		T212	1
all_pins[10]	values[0x0]	6538928	1			T1	2		T4	1		T2	2
all_pins[10]	values[0x1]	100	1			T83	2		T84	1		T85	2
all_pins[10]	transitions[0x0=>0x1]	79	1			T83	1		T84	1		T85	2
all_pins[10]	transitions[0x1=>0x0]	6294	1			T83	3		T85	4		T86	2
all_pins[11]	values[0x0]	6532713	1			T1	2		T4	1		T2	2
all_pins[11]	values[0x1]	6315	1			T83	4		T85	4		T86	2
all_pins[11]	transitions[0x0=>0x1]	6278	1			T83	3		T85	2		T86	2
all_pins[11]	transitions[0x1=>0x0]	536	1			T2	1		T9	1		T83	4