Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	434	1			T14	2		T6	1		T33	2
auto[ReadAddrCrossIntoMailbox]	274	1			T14	4		T6	1		T8	3
auto[ReadAddrCrossOutOfMailbox]	308	1			T6	1		T33	2		T8	3
auto[ReadAddrCrossAllMailbox]	226	1			T28	3		T30	5		T256	2
auto[ReadAddrOutsideMailbox]	3327	1			T11	2		T12	2		T33	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2346

1

T11

1

T12

1

T14

3

auto[1]

2223

1

T11

1

T12

1

T14

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	752	1			T8	6		T24	1		T34	2
read_ops[0x0b]	778	1			T8	6		T24	2		T25	6
read_ops[0x3b]	698	1			T12	2		T6	1		T8	9
read_ops[0x6b]	766	1			T8	10		T32	2		T28	12
read_ops[0xbb]	866	1			T11	2		T6	1		T8	9
read_ops[0xeb]	709	1			T14	6		T6	1		T33	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T240	1		T236	2		T250	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T30	1		T240	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T261	2		T38	2		T309	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T76	1		T261	2		T309	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T8	2		T28	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T30	1		T76	2		T261	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T30	2		T261	1		T38	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T28	1		T261	1		T250	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T8	1		T24	1		T34	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	273	1			T8	3		T34	1		T32	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T28	1		T30	1		T240	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T240	1		T256	1		T76	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T256	1		T36	1		T77	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T256	1		T76	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T30	1		T40	1		T88	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T38	1		T39	2		T40	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T30	1		T256	1		T79	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T256	1		T39	1		T234	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T8	5		T24	1		T25	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T8	1		T24	1		T25	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	17	1			T28	3		T77	1		T310	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T39	2		T79	1		T231	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T28	1		T261	1		T39	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T30	1		T261	1		T227	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T6	1		T28	1		T38	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T28	3		T36	1		T38	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T38	1		T39	3		T231	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T40	1		T263	1		T310	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T12	1		T8	2		T24	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	262	1			T12	1		T8	7		T28	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T8	1		T240	1		T231	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T240	1		T38	1		T39	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T28	1		T250	1		T235	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T8	1		T28	1		T36	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T8	1		T30	2		T77	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T28	1		T38	1		T216	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T36	1		T272	1		T245	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T28	2		T36	1		T38	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T8	6		T32	1		T28	6
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	254	1			T8	1		T32	1		T28	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	50	1			T8	1		T240	1		T38	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T6	1		T30	2		T240	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T8	1		T30	1		T39	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T40	2		T154	1		T227	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T28	1		T261	1		T38	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T30	1		T261	1		T38	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T30	1		T261	1		T40	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T261	1		T38	1		T247	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	331	1			T11	1		T8	5		T24	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	269	1			T11	1		T8	2		T220	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T14	1		T33	1		T34	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T14	1		T33	1		T34	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T14	2		T8	1		T40	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T14	2		T6	1		T28	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T33	1		T76	1		T36	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T33	1		T30	1		T79	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T40	1		T77	3		T154	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T30	1		T38	1		T247	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	263	1			T33	1		T8	1		T32	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	258	1			T33	1		T8	4		T24	2