Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2770	1			T26	18		T8	20		T24	40
values[1]	3516	1			T8	20		T34	6		T28	86
values[2]	4408	1			T17	12		T23	12		T12	8
values[3]	3966	1			T8	20		T32	18		T143	8
values[4]	4071	1			T6	20		T8	47		T28	51
values[5]	3710	1			T11	20		T45	2		T28	101
values[6]	3634	1			T14	6		T33	6		T275	2
values[7]	3153	1			T220	4		T28	33		T30	92

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3788	1			T14	6		T29	26		T34	6
values[1]	3340	1			T8	60		T32	18		T27	18
values[2]	3506	1			T23	12		T45	2		T143	8
values[3]	3904	1			T17	12		T11	20		T33	6
values[4]	3397	1			T28	26		T30	88		T31	40
values[5]	4010	1			T8	57		T24	40		T220	4
values[6]	3697	1			T6	20		T8	108		T275	2
values[7]	3586	1			T12	8		T26	18		T8	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28731

1

T17

12

T23

12

T11

20

auto[1]

497

1

T8

3

T27

4

T28

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	325	1			T36	20		T234	67		T237	40
auto[0]	values[0]	values[1]	285	1			T8	20		T27	14		T30	25
auto[0]	values[0]	values[2]	159	1			T38	20		T235	28		T243	19
auto[0]	values[0]	values[3]	306	1			T227	20		T247	20		T286	20
auto[0]	values[0]	values[4]	272	1			T294	54		T308	18		T311	80
auto[0]	values[0]	values[5]	350	1			T24	40		T239	8		T246	46
auto[0]	values[0]	values[6]	422	1			T241	71		T39	25		T234	38
auto[0]	values[0]	values[7]	597	1			T26	18		T35	18		T213	8
auto[0]	values[1]	values[0]	413	1			T34	6		T28	30		T229	14
auto[0]	values[1]	values[1]	195	1			T8	20		T28	28		T305	24
auto[0]	values[1]	values[2]	321	1			T260	18		T38	51		T235	22
auto[0]	values[1]	values[3]	580	1			T30	20		T299	26		T237	24
auto[0]	values[1]	values[4]	584	1			T28	26		T30	20		T264	26
auto[0]	values[1]	values[5]	347	1			T36	20		T254	18		T227	20
auto[0]	values[1]	values[6]	591	1			T30	20		T256	18		T40	20
auto[0]	values[1]	values[7]	439	1			T30	19		T234	84		T289	20
auto[0]	values[2]	values[0]	896	1			T29	26		T298	6		T36	20
auto[0]	values[2]	values[1]	438	1			T8	20		T40	20		T232	33
auto[0]	values[2]	values[2]	554	1			T23	12		T28	19		T30	20
auto[0]	values[2]	values[3]	591	1			T17	12		T8	110		T39	20
auto[0]	values[2]	values[4]	314	1			T38	20		T247	66		T312	24
auto[0]	values[2]	values[5]	518	1			T8	37		T76	20		T39	20
auto[0]	values[2]	values[6]	575	1			T8	60		T284	4		T38	57
auto[0]	values[2]	values[7]	460	1			T12	8		T8	20		T30	49
auto[0]	values[3]	values[0]	337	1			T252	10		T216	16		T227	96
auto[0]	values[3]	values[1]	619	1			T32	18		T39	20		T40	20
auto[0]	values[3]	values[2]	578	1			T143	8		T285	12		T77	31
auto[0]	values[3]	values[3]	497	1			T76	18		T39	20		T313	79
auto[0]	values[3]	values[4]	548	1			T154	20		T237	101		T245	33
auto[0]	values[3]	values[5]	575	1			T8	20		T39	20		T79	20
auto[0]	values[3]	values[6]	349	1			T234	77		T253	20		T286	20
auto[0]	values[3]	values[7]	390	1			T283	4		T28	26		T30	18
auto[0]	values[4]	values[0]	480	1			T254	20		T227	119		T314	2
auto[0]	values[4]	values[1]	405	1			T28	20		T236	12		T231	22
auto[0]	values[4]	values[2]	385	1			T28	31		T30	20		T38	20
auto[0]	values[4]	values[3]	605	1			T309	2		T307	4		T315	4
auto[0]	values[4]	values[4]	527	1			T30	48		T31	19		T316	6
auto[0]	values[4]	values[5]	643	1			T30	54		T36	24		T39	20
auto[0]	values[4]	values[6]	459	1			T6	20		T8	47		T301	67
auto[0]	values[4]	values[7]	502	1			T30	20		T237	20		T243	20
auto[0]	values[5]	values[0]	436	1			T28	29		T30	20		T238	26
auto[0]	values[5]	values[1]	478	1			T28	19		T38	64		T77	20
auto[0]	values[5]	values[2]	570	1			T45	2		T227	19		T235	25
auto[0]	values[5]	values[3]	347	1			T11	20		T77	34		T254	31
auto[0]	values[5]	values[4]	299	1			T40	26		T317	4		T267	18
auto[0]	values[5]	values[5]	669	1			T30	33		T216	54		T77	111
auto[0]	values[5]	values[6]	410	1			T28	50		T76	20		T227	20
auto[0]	values[5]	values[7]	432	1			T38	20		T39	32		T79	19
auto[0]	values[6]	values[0]	497	1			T14	6		T28	27		T30	20
auto[0]	values[6]	values[1]	473	1			T38	20		T296	6		T40	43
auto[0]	values[6]	values[2]	420	1			T30	22		T36	23		T38	20
auto[0]	values[6]	values[3]	537	1			T33	6		T240	18		T297	26
auto[0]	values[6]	values[4]	417	1			T215	34		T77	37		T318	8
auto[0]	values[6]	values[5]	398	1			T40	22		T319	20		T231	18
auto[0]	values[6]	values[6]	525	1			T275	2		T25	22		T39	20
auto[0]	values[6]	values[7]	306	1			T295	16		T39	56		T259	28
auto[0]	values[7]	values[0]	334	1			T38	28		T40	18		T79	36
auto[0]	values[7]	values[1]	383	1			T28	33		T76	20		T231	17
auto[0]	values[7]	values[2]	464	1			T30	32		T250	16		T77	20
auto[0]	values[7]	values[3]	374	1			T270	24		T291	18		T38	40
auto[0]	values[7]	values[4]	384	1			T30	20		T31	20		T38	37
auto[0]	values[7]	values[5]	443	1			T220	4		T30	20		T37	32
auto[0]	values[7]	values[6]	311	1			T306	14		T40	21		T154	21
auto[0]	values[7]	values[7]	393	1			T30	19		T217	10		T40	22
auto[1]	values[0]	values[0]	5	1			T234	1		T268	2		T320	1
auto[1]	values[0]	values[1]	6	1			T27	4		T253	1		T289	1
auto[1]	values[0]	values[2]	6	1			T235	1		T243	1		T289	2
auto[1]	values[0]	values[3]	7	1			T321	3		T322	2		T323	2
auto[1]	values[0]	values[4]	4	1			T308	2		T324	1		T325	1
auto[1]	values[0]	values[5]	4	1			T321	3		T326	1		-	-
auto[1]	values[0]	values[6]	4	1			T237	3		T273	1		-	-
auto[1]	values[0]	values[7]	18	1			T35	4		T39	1		T77	2
auto[1]	values[1]	values[0]	5	1			T28	1		T132	3		T327	1
auto[1]	values[1]	values[1]	1	1			T28	1		-	-		-	-
auto[1]	values[1]	values[2]	6	1			T38	4		T235	2		-	-
auto[1]	values[1]	values[3]	10	1			T237	2		T324	5		T328	1
auto[1]	values[1]	values[4]	11	1			T36	2		T77	2		T234	2
auto[1]	values[1]	values[5]	6	1			T254	2		T88	2		T329	2
auto[1]	values[1]	values[6]	5	1			T77	1		T330	1		T311	2
auto[1]	values[1]	values[7]	2	1			T30	1		T331	1		-	-
auto[1]	values[2]	values[0]	19	1			T38	6		T235	1		T243	1
auto[1]	values[2]	values[1]	6	1			T332	2		T333	3		T334	1
auto[1]	values[2]	values[2]	5	1			T28	1		T237	1		T243	1
auto[1]	values[2]	values[3]	7	1			T8	2		T335	2		T336	1
auto[1]	values[2]	values[4]	4	1			T247	1		T255	1		T337	2
auto[1]	values[2]	values[5]	7	1			T77	1		T234	1		T228	2
auto[1]	values[2]	values[6]	7	1			T8	1		T248	3		T338	2
auto[1]	values[2]	values[7]	7	1			T132	2		T273	1		T328	1
auto[1]	values[3]	values[0]	16	1			T216	4		T227	4		T339	1
auto[1]	values[3]	values[1]	12	1			T231	2		T340	2		T330	2
auto[1]	values[3]	values[2]	7	1			T79	4		T237	1		T245	1
auto[1]	values[3]	values[3]	9	1			T76	2		T289	1		T321	5
auto[1]	values[3]	values[4]	8	1			T242	2		T329	2		T325	1
auto[1]	values[3]	values[5]	9	1			T231	1		T237	1		T132	2
auto[1]	values[3]	values[6]	10	1			T234	1		T246	3		T338	1
auto[1]	values[3]	values[7]	2	1			T30	2		-	-		-	-
auto[1]	values[4]	values[0]	3	1			T227	2		T334	1		-	-
auto[1]	values[4]	values[1]	8	1			T235	1		T341	2		T327	3
auto[1]	values[4]	values[2]	2	1			T154	1		T334	1		-	-
auto[1]	values[4]	values[3]	12	1			T342	2		T267	2		T343	1
auto[1]	values[4]	values[4]	12	1			T31	1		T77	1		T79	2
auto[1]	values[4]	values[5]	12	1			T234	1		T227	3		T235	1
auto[1]	values[4]	values[6]	5	1			T331	4		T311	1		-	-
auto[1]	values[4]	values[7]	11	1			T253	3		T320	3		T324	2
auto[1]	values[5]	values[0]	9	1			T28	2		T234	1		T269	2
auto[1]	values[5]	values[1]	11	1			T28	1		T330	2		T322	1
auto[1]	values[5]	values[2]	15	1			T227	1		T311	1		T329	2
auto[1]	values[5]	values[3]	5	1			T254	1		T247	1		T132	2
auto[1]	values[5]	values[4]	5	1			T40	1		T267	2		T331	1
auto[1]	values[5]	values[5]	15	1			T30	2		T77	3		T234	3
auto[1]	values[5]	values[6]	3	1			T273	2		T325	1		-	-
auto[1]	values[5]	values[7]	6	1			T79	1		T330	2		T338	1
auto[1]	values[6]	values[0]	6	1			T28	1		T88	1		T132	1
auto[1]	values[6]	values[1]	10	1			T344	2		T132	3		T255	1
auto[1]	values[6]	values[2]	6	1			T242	3		T273	1		T308	1
auto[1]	values[6]	values[3]	14	1			T231	2		T237	2		T246	1
auto[1]	values[6]	values[4]	2	1			T345	1		T245	1		-	-
auto[1]	values[6]	values[5]	9	1			T40	1		T231	2		T327	1
auto[1]	values[6]	values[6]	7	1			T79	1		T235	2		T321	2
auto[1]	values[6]	values[7]	7	1			T39	1		T77	1		T132	4
auto[1]	values[7]	values[0]	7	1			T38	1		T40	2		T267	2
auto[1]	values[7]	values[1]	10	1			T231	3		T225	1		T245	1
auto[1]	values[7]	values[2]	8	1			T346	2		T242	1		T324	3
auto[1]	values[7]	values[3]	3	1			T330	1		T324	2		-	-
auto[1]	values[7]	values[4]	6	1			T231	2		T88	1		T242	1
auto[1]	values[7]	values[5]	5	1			T37	4		T340	1		-	-
auto[1]	values[7]	values[6]	14	1			T40	3		T154	3		T227	3
auto[1]	values[7]	values[7]	14	1			T30	1		T40	1		T77	2