Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2348

1

T22

19

T100

3

T6

1

auto[1]

2350

1

T22

23

T100

1

T6

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2321

1

T100

4

T6

3

T24

10

auto[1]

2377

1

T22

42

T42

29

T121

23

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3839

1

T22

42

T100

3

T6

3

auto[1]

859

1

T100

1

T24

3

T124

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	920	1			T22	8		T100	1		T6	1
valid[1]	915	1			T22	10		T6	1		T24	3
valid[2]	990	1			T22	9		T100	1		T24	1
valid[3]	955	1			T22	7		T24	1		T42	8
valid[4]	918	1			T22	8		T100	2		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	143	1			T100	1		T6	1		T24	2
auto[0]	auto[0]	valid[0]	auto[1]	235	1			T22	2		T42	3		T121	3
auto[0]	auto[0]	valid[1]	auto[0]	137	1			T63	2		T28	1		T31	2
auto[0]	auto[0]	valid[1]	auto[1]	222	1			T22	9		T42	4		T121	3
auto[0]	auto[0]	valid[2]	auto[0]	152	1			T24	1		T61	1		T63	2
auto[0]	auto[0]	valid[2]	auto[1]	239	1			T22	5		T42	3		T121	2
auto[0]	auto[0]	valid[3]	auto[0]	166	1			T24	1		T63	2		T30	1
auto[0]	auto[0]	valid[3]	auto[1]	241	1			T22	3		T42	3		T121	2
auto[0]	auto[0]	valid[4]	auto[0]	154	1			T100	1		T63	2		T28	1
auto[0]	auto[0]	valid[4]	auto[1]	238	1			T42	1		T121	3		T133	2
auto[0]	auto[1]	valid[0]	auto[0]	143	1			T63	3		T28	1		T131	1
auto[0]	auto[1]	valid[0]	auto[1]	232	1			T22	6		T42	3		T133	2
auto[0]	auto[1]	valid[1]	auto[0]	146	1			T6	1		T24	2		T61	1
auto[0]	auto[1]	valid[1]	auto[1]	255	1			T22	1		T42	2		T121	2
auto[0]	auto[1]	valid[2]	auto[0]	146	1			T100	1		T61	2		T63	2
auto[0]	auto[1]	valid[2]	auto[1]	264	1			T22	4		T42	1		T121	4
auto[0]	auto[1]	valid[3]	auto[0]	132	1			T61	1		T63	2		T28	5
auto[0]	auto[1]	valid[3]	auto[1]	236	1			T22	4		T42	5		T121	1
auto[0]	auto[1]	valid[4]	auto[0]	143	1			T6	1		T24	1		T62	1
auto[0]	auto[1]	valid[4]	auto[1]	215	1			T22	8		T42	4		T121	3
auto[1]	auto[0]	valid[0]	auto[0]	87	1			T28	3		T31	1		T218	1
auto[1]	auto[0]	valid[1]	auto[0]	84	1			T24	1		T63	1		T28	1
auto[1]	auto[0]	valid[2]	auto[0]	90	1			T63	3		T28	2		T131	1
auto[1]	auto[0]	valid[3]	auto[0]	78	1			T61	1		T31	3		T76	1
auto[1]	auto[0]	valid[4]	auto[0]	82	1			T100	1		T24	2		T28	2
auto[1]	auto[1]	valid[0]	auto[0]	80	1			T124	1		T61	1		T63	2
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T61	1		T31	1		T353	1
auto[1]	auto[1]	valid[2]	auto[0]	99	1			T62	1		T28	1		T131	2
auto[1]	auto[1]	valid[3]	auto[0]	102	1			T63	1		T31	1		T218	1
auto[1]	auto[1]	valid[4]	auto[0]	86	1			T28	1		T218	1		T353	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal