Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	72	2	70	97.22

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	72	2	70	97.22	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	456	1			T83	10		T84	4		T85	10
all_values[1]	456	1			T83	10		T84	4		T85	10
all_values[2]	456	1			T83	10		T84	4		T85	10
all_values[3]	456	1			T83	10		T84	4		T85	10
all_values[4]	456	1			T83	10		T84	4		T85	10
all_values[5]	456	1			T83	10		T84	4		T85	10
all_values[6]	456	1			T83	10		T84	4		T85	10
all_values[7]	456	1			T83	10		T84	4		T85	10
all_values[8]	456	1			T83	10		T84	4		T85	10
all_values[9]	456	1			T83	10		T84	4		T85	10
all_values[10]	456	1			T83	10		T84	4		T85	10
all_values[11]	456	1			T83	10		T84	4		T85	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2891

1

T83

59

T84

30

T85

51

auto[1]

2581

1

T83

61

T84

18

T85

69

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2070

1

T83

41

T84

21

T85

33

auto[1]

3402

1

T83

79

T84

27

T85

87

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3099

1

T83

63

T84

32

T85

60

auto[1]

2373

1

T83

57

T84

16

T85

60

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	2	70	97.22	2
Automatically Generated Cross Bins	72	2	70	97.22	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[11]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	78	1			T83	2		T86	2		T212	1
all_values[0]	auto[0]	auto[0]	auto[1]	49	1			T83	1		T84	1		T85	2
all_values[0]	auto[0]	auto[1]	auto[0]	88	1			T83	1		T84	2		T85	1
all_values[0]	auto[0]	auto[1]	auto[1]	48	1			T83	1		T85	2		T199	1
all_values[0]	auto[1]	auto[0]	auto[1]	90	1			T83	2		T84	1		T85	3
all_values[0]	auto[1]	auto[1]	auto[1]	103	1			T83	3		T85	2		T164	3
all_values[1]	auto[0]	auto[0]	auto[0]	97	1			T84	1		T85	3		T86	3
all_values[1]	auto[0]	auto[0]	auto[1]	41	1			T212	1		T199	1		T200	1
all_values[1]	auto[0]	auto[1]	auto[0]	71	1			T83	3		T84	1		T85	3
all_values[1]	auto[0]	auto[1]	auto[1]	58	1			T83	3		T84	1		T164	1
all_values[1]	auto[1]	auto[0]	auto[1]	96	1			T83	2		T85	1		T86	1
all_values[1]	auto[1]	auto[1]	auto[1]	93	1			T83	2		T84	1		T85	3
all_values[2]	auto[0]	auto[0]	auto[0]	88	1			T83	4		T84	1		T86	2
all_values[2]	auto[0]	auto[0]	auto[1]	41	1			T86	2		T212	1		T200	1
all_values[2]	auto[0]	auto[1]	auto[0]	71	1			T83	2		T84	1		T86	1
all_values[2]	auto[0]	auto[1]	auto[1]	55	1			T84	1		T85	3		T164	1
all_values[2]	auto[1]	auto[0]	auto[1]	110	1			T83	1		T85	5		T86	1
all_values[2]	auto[1]	auto[1]	auto[1]	91	1			T83	3		T84	1		T85	2
all_values[3]	auto[0]	auto[0]	auto[0]	72	1			T83	2		T85	3		T86	1
all_values[3]	auto[0]	auto[0]	auto[1]	38	1			T83	1		T84	1		T86	1
all_values[3]	auto[0]	auto[1]	auto[0]	64	1			T85	4		T86	3		T212	1
all_values[3]	auto[0]	auto[1]	auto[1]	50	1			T83	1		T164	2		T212	2
all_values[3]	auto[1]	auto[0]	auto[1]	133	1			T83	2		T84	2		T85	1
all_values[3]	auto[1]	auto[1]	auto[1]	99	1			T83	4		T84	1		T85	2
all_values[4]	auto[0]	auto[0]	auto[0]	106	1			T83	1		T84	1		T164	2
all_values[4]	auto[0]	auto[0]	auto[1]	47	1			T84	1		T85	1		T86	1
all_values[4]	auto[0]	auto[1]	auto[0]	71	1			T83	3		T85	1		T86	2
all_values[4]	auto[0]	auto[1]	auto[1]	50	1			T85	5		T86	1		T212	1
all_values[4]	auto[1]	auto[0]	auto[1]	108	1			T83	5		T84	2		T85	2
all_values[4]	auto[1]	auto[1]	auto[1]	74	1			T83	1		T85	1		T86	3
all_values[5]	auto[0]	auto[0]	auto[0]	95	1			T83	1		T84	2		T85	1
all_values[5]	auto[0]	auto[0]	auto[1]	42	1			T83	2		T85	3		T164	1
all_values[5]	auto[0]	auto[1]	auto[0]	67	1			T83	1		T85	2		T199	2
all_values[5]	auto[0]	auto[1]	auto[1]	48	1			T83	2		T84	1		T85	1
all_values[5]	auto[1]	auto[0]	auto[1]	109	1			T83	3		T85	2		T86	1
all_values[5]	auto[1]	auto[1]	auto[1]	95	1			T83	1		T84	1		T85	1
all_values[6]	auto[0]	auto[0]	auto[0]	83	1			T83	2		T164	1		T212	1
all_values[6]	auto[0]	auto[0]	auto[1]	51	1			T84	1		T85	1		T201	1
all_values[6]	auto[0]	auto[1]	auto[0]	73	1			T83	5		T84	1		T85	2
all_values[6]	auto[0]	auto[1]	auto[1]	45	1			T85	1		T86	1		T212	3
all_values[6]	auto[1]	auto[0]	auto[1]	107	1			T83	2		T84	1		T85	3
all_values[6]	auto[1]	auto[1]	auto[1]	97	1			T83	1		T84	1		T85	3
all_values[7]	auto[0]	auto[0]	auto[0]	102	1			T83	1		T84	2		T86	1
all_values[7]	auto[0]	auto[0]	auto[1]	36	1			T83	2		T85	1		T212	1
all_values[7]	auto[0]	auto[1]	auto[0]	79	1			T83	1		T164	1		T212	1
all_values[7]	auto[0]	auto[1]	auto[1]	47	1			T83	1		T84	1		T85	1
all_values[7]	auto[1]	auto[0]	auto[1]	86	1			T83	1		T85	3		T86	1
all_values[7]	auto[1]	auto[1]	auto[1]	106	1			T83	4		T84	1		T85	5
all_values[8]	auto[0]	auto[0]	auto[0]	96	1			T83	4		T84	2		T85	1
all_values[8]	auto[0]	auto[0]	auto[1]	41	1			T83	1		T84	1		T85	2
all_values[8]	auto[0]	auto[1]	auto[0]	81	1			T83	1		T86	1		T164	3
all_values[8]	auto[0]	auto[1]	auto[1]	47	1			T85	1		T86	2		T212	2
all_values[8]	auto[1]	auto[0]	auto[1]	112	1			T83	2		T84	1		T85	1
all_values[8]	auto[1]	auto[1]	auto[1]	79	1			T83	2		T85	5		T86	1
all_values[9]	auto[0]	auto[0]	auto[0]	87	1			T84	3		T85	1		T86	1
all_values[9]	auto[0]	auto[0]	auto[1]	58	1			T83	3		T199	2		T200	1
all_values[9]	auto[0]	auto[1]	auto[0]	71	1			T83	1		T84	1		T85	2
all_values[9]	auto[0]	auto[1]	auto[1]	43	1			T83	2		T85	1		T86	1
all_values[9]	auto[1]	auto[0]	auto[1]	108	1			T83	2		T85	2		T86	3
all_values[9]	auto[1]	auto[1]	auto[1]	89	1			T83	2		T85	4		T212	3
all_values[10]	auto[0]	auto[0]	auto[0]	91	1			T85	4		T164	1		T212	2
all_values[10]	auto[0]	auto[0]	auto[1]	50	1			T83	2		T84	2		T212	1
all_values[10]	auto[0]	auto[1]	auto[0]	78	1			T83	2		T85	1		T86	4
all_values[10]	auto[0]	auto[1]	auto[1]	44	1			T85	2		T212	1		T199	1
all_values[10]	auto[1]	auto[0]	auto[1]	110	1			T83	4		T84	1		T85	1
all_values[10]	auto[1]	auto[1]	auto[1]	83	1			T83	2		T84	1		T85	2
all_values[11]	auto[0]	auto[0]	auto[0]	136	1			T83	1		T84	2		T86	2
all_values[11]	auto[0]	auto[1]	auto[0]	125	1			T83	3		T84	1		T85	4
all_values[11]	auto[1]	auto[0]	auto[1]	97	1			T83	3		T84	1		T85	4
all_values[11]	auto[1]	auto[1]	auto[1]	98	1			T83	3		T85	2		T86	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal