Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59573

1

T100

100

T101

14

T6

53

auto[1]

24845

1

T22

554

T6

7

T42

323

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62447

1

T22

554

T100

60

T101

6

auto[1]

21971

1

T100

40

T101

8

T6

15

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	43546	1			T22	286		T100	50		T101	7
others[1]	7142	1			T22	51		T100	8		T6	10
others[2]	7113	1			T22	53		T100	8		T6	2
others[3]	8014	1			T22	51		T100	13		T101	2
interest[1]	4734	1			T22	32		T100	6		T101	2
interest[4]	28628	1			T22	182		T100	29		T101	5
interest[64]	13869	1			T22	81		T100	15		T101	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	19345	1			T100	29		T101	3		T6	14
auto[0]	auto[0]	others[1]	3172	1			T100	5		T6	6		T24	17
auto[0]	auto[0]	others[2]	3172	1			T100	5		T6	1		T24	10
auto[0]	auto[0]	others[3]	3653	1			T100	7		T6	5		T24	15
auto[0]	auto[0]	interest[1]	2112	1			T100	4		T101	2		T6	6
auto[0]	auto[0]	interest[4]	12683	1			T100	14		T101	3		T6	11
auto[0]	auto[0]	interest[64]	6148	1			T100	10		T101	1		T6	6
auto[0]	auto[1]	others[0]	12891	1			T22	286		T6	3		T42	169
auto[0]	auto[1]	others[1]	2110	1			T22	51		T42	24		T121	16
auto[0]	auto[1]	others[2]	2080	1			T22	53		T6	1		T42	33
auto[0]	auto[1]	others[3]	2285	1			T22	51		T6	2		T42	24
auto[0]	auto[1]	interest[1]	1406	1			T22	32		T42	27		T121	13
auto[0]	auto[1]	interest[4]	8506	1			T22	182		T6	1		T42	111
auto[0]	auto[1]	interest[64]	4073	1			T22	81		T6	1		T42	46
auto[1]	auto[0]	others[0]	11310	1			T100	21		T101	4		T6	5
auto[1]	auto[0]	others[1]	1860	1			T100	3		T6	4		T24	5
auto[1]	auto[0]	others[2]	1861	1			T100	3		T24	7		T123	1
auto[1]	auto[0]	others[3]	2076	1			T100	6		T101	2		T6	1
auto[1]	auto[0]	interest[1]	1216	1			T100	2		T6	3		T24	2
auto[1]	auto[0]	interest[4]	7439	1			T100	15		T101	2		T6	4
auto[1]	auto[0]	interest[64]	3648	1			T100	5		T101	2		T6	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal