Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::all_modes_cg

Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	5	0	5	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_tpm_enabled	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	5	0	5	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[GenericMode]	5746242	1			T2	3718		T5	1405		T9	43569
auto[FlashMode]	91111	1			T22	554		T13	30		T100	100
auto[PassthroughMode]	53328	1			T17	14		T23	34		T11	20

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Summary for Variable cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tpm_enabled

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5647633

1

T2

3718

T5

1405

T9

43569

auto[1]

243048

1

T22

554

T100

100

T101

14

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Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	5	0	5	100.00
Automatically Generated Cross Bins	5	0	5	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_mode	cp_tpm_enabled	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[GenericMode]	auto[0]	5623352	1			T2	3718		T5	1405		T9	43569
auto[FlashMode]	auto[0]	7619	1			T13	30		T7	303		T51	29
auto[FlashMode]	auto[1]	83492	1			T22	554		T100	100		T101	14
auto[PassthroughMode]	auto[0]	16662	1			T17	14		T23	34		T11	20
auto[PassthroughMode]	auto[1]	36666	1			T6	47		T24	257		T28	971

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded