Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6566482	1			T4	1		T1	2		T2	2
all_values[1]	6566482	1			T4	1		T1	2		T2	2
all_values[2]	6566482	1			T4	1		T1	2		T2	2
all_values[3]	6566482	1			T4	1		T1	2		T2	2
all_values[4]	6566482	1			T4	1		T1	2		T2	2
all_values[5]	6566482	1			T4	1		T1	2		T2	2
all_values[6]	6566482	1			T4	1		T1	2		T2	2
all_values[7]	6566482	1			T4	1		T1	2		T2	2
all_values[8]	6566482	1			T4	1		T1	2		T2	2
all_values[9]	6566482	1			T4	1		T1	2		T2	2
all_values[10]	6566482	1			T4	1		T1	2		T2	2
all_values[11]	6566482	1			T4	1		T1	2		T2	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75928546

1

T4

12

T1

16

T2

8

auto[1]

2869238

1

T1

8

T2

16

T3

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78739731

1

T4

12

T1

24

T2

24

auto[1]

58053

1

T6

367

T7

365

T57

41

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6240516	1			T4	1		T1	2		T2	2
all_values[0]	auto[0]	auto[1]	102	1			T57	3		T58	1		T59	2
all_values[0]	auto[1]	auto[0]	325748	1			T57	2		T58	3		T59	1
all_values[0]	auto[1]	auto[1]	116	1			T57	2		T58	1		T60	3
all_values[1]	auto[0]	auto[0]	6313534	1			T4	1		T10	1		T3	2
all_values[1]	auto[0]	auto[1]	105	1			T57	2		T58	2		T59	1
all_values[1]	auto[1]	auto[0]	252739	1			T1	2		T2	2		T57	5
all_values[1]	auto[1]	auto[1]	104	1			T57	1		T59	1		T130	3
all_values[2]	auto[0]	auto[0]	6400717	1			T4	1		T10	1		T27	1
all_values[2]	auto[0]	auto[1]	93	1			T57	2		T60	1		T130	4
all_values[2]	auto[1]	auto[0]	165575	1			T1	2		T2	2		T3	2
all_values[2]	auto[1]	auto[1]	97	1			T57	2		T58	2		T59	1
all_values[3]	auto[0]	auto[0]	6168383	1			T4	1		T1	2		T10	1
all_values[3]	auto[0]	auto[1]	95	1			T57	1		T58	1		T59	1
all_values[3]	auto[1]	auto[0]	397897	1			T2	2		T3	2		T57	5
all_values[3]	auto[1]	auto[1]	107	1			T57	1		T58	2		T59	1
all_values[4]	auto[0]	auto[0]	6403882	1			T4	1		T1	2		T10	1
all_values[4]	auto[0]	auto[1]	131	1			T57	1		T58	1		T59	2
all_values[4]	auto[1]	auto[0]	162378	1			T2	2		T3	2		T11	2
all_values[4]	auto[1]	auto[1]	91	1			T57	3		T58	2		T59	1
all_values[5]	auto[0]	auto[0]	6126072	1			T4	1		T10	1		T27	1
all_values[5]	auto[0]	auto[1]	117	1			T57	5		T60	2		T130	2
all_values[5]	auto[1]	auto[0]	440203	1			T1	2		T2	2		T3	2
all_values[5]	auto[1]	auto[1]	90	1			T57	2		T58	1		T60	1
all_values[6]	auto[0]	auto[0]	6204928	1			T4	1		T1	2		T10	1
all_values[6]	auto[0]	auto[1]	32458	1			T6	196		T7	242		T57	3
all_values[6]	auto[1]	auto[0]	327628	1			T2	2		T3	2		T57	1
all_values[6]	auto[1]	auto[1]	1468	1			T57	1		T58	2		T59	1
all_values[7]	auto[0]	auto[0]	6429541	1			T4	1		T1	2		T2	2
all_values[7]	auto[0]	auto[1]	16116	1			T6	105		T7	88		T59	1
all_values[7]	auto[1]	auto[0]	120327	1			T3	2		T57	1		T58	1
all_values[7]	auto[1]	auto[1]	498	1			T57	2		T58	2		T60	1
all_values[8]	auto[0]	auto[0]	6395438	1			T4	1		T10	1		T3	2
all_values[8]	auto[0]	auto[1]	5320	1			T6	66		T7	35		T57	2
all_values[8]	auto[1]	auto[0]	165586	1			T1	2		T2	2		T57	4
all_values[8]	auto[1]	auto[1]	138	1			T57	1		T58	2		T59	1
all_values[9]	auto[0]	auto[0]	6444892	1			T4	1		T1	2		T2	2
all_values[9]	auto[0]	auto[1]	116	1			T57	3		T58	1		T60	1
all_values[9]	auto[1]	auto[0]	121362	1			T3	2		T11	2		T58	1
all_values[9]	auto[1]	auto[1]	112	1			T57	3		T58	3		T59	1
all_values[10]	auto[0]	auto[0]	6487187	1			T4	1		T1	2		T2	2
all_values[10]	auto[0]	auto[1]	113	1			T58	1		T60	6		T130	1
all_values[10]	auto[1]	auto[0]	79072	1			T3	2		T11	2		T57	3
all_values[10]	auto[1]	auto[1]	110	1			T59	4		T60	1		T130	3
all_values[11]	auto[0]	auto[0]	6258421	1			T4	1		T1	2		T10	1
all_values[11]	auto[0]	auto[1]	269	1			T59	1		T60	2		T130	3
all_values[11]	auto[1]	auto[0]	307705	1			T2	2		T57	1		T58	1
all_values[11]	auto[1]	auto[1]	87	1			T57	1		T59	2		T60	1