Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.10 99.01 96.33 98.63 92.06 98.05 95.86 99.76


Total tests in report: 1786
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
78.16 78.16 96.64 96.64 87.47 87.47 67.81 67.81 75.41 75.41 95.04 95.04 82.72 82.72 42.02 42.02 /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1413006458
85.49 7.33 98.28 1.64 92.63 5.16 89.33 21.53 93.44 18.03 97.24 2.20 84.05 1.33 43.45 1.43 /workspace/coverage/default/15.spi_device_extreme_fifo_size.1230083371
88.12 2.63 98.39 0.10 93.39 0.76 89.63 0.29 93.44 0.00 97.49 0.25 84.49 0.44 59.98 16.53 /workspace/coverage/default/23.spi_device_stress_all.3066185574
89.91 1.80 98.41 0.02 93.58 0.19 90.80 1.17 93.44 0.00 97.53 0.03 93.80 9.31 61.84 1.86 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.523111523
91.24 1.33 98.43 0.02 93.64 0.06 90.80 0.00 93.44 0.00 97.54 0.02 93.80 0.00 71.03 9.19 /workspace/coverage/default/35.spi_device_stress_all.2543176318
92.50 1.26 98.83 0.40 93.91 0.27 92.76 1.96 93.44 0.00 97.54 0.00 93.80 0.00 77.23 6.19 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.51060615
93.43 0.93 98.83 0.00 93.91 0.00 92.76 0.00 93.44 0.00 97.54 0.00 93.80 0.00 83.75 6.53 /workspace/coverage/default/16.spi_device_flash_and_tpm.3357478383
93.99 0.56 98.84 0.01 93.91 0.00 96.67 3.91 93.44 0.00 97.54 0.00 93.80 0.00 83.75 0.00 /workspace/coverage/default/0.spi_device_ram_cfg.3395319302
94.40 0.41 98.84 0.00 93.96 0.05 96.67 0.00 93.44 0.00 97.58 0.03 93.80 0.00 86.52 2.76 /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1054044056
94.74 0.34 98.89 0.06 94.05 0.09 98.04 1.37 93.44 0.00 97.63 0.05 94.09 0.30 87.04 0.52 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1048755363
95.05 0.31 98.91 0.02 94.57 0.52 98.24 0.20 93.44 0.00 97.65 0.02 94.09 0.00 88.47 1.43 /workspace/coverage/default/38.spi_device_stress_all.713303925
95.35 0.30 98.95 0.04 94.62 0.05 98.24 0.00 95.08 1.64 97.70 0.05 94.09 0.00 88.80 0.33 /workspace/coverage/default/44.spi_device_stress_all.3006297698
95.59 0.23 99.06 0.11 95.05 0.43 98.24 0.00 95.08 0.00 97.85 0.15 94.68 0.59 89.14 0.33 /workspace/coverage/default/34.spi_device_flash_mode.636488188
95.81 0.22 99.06 0.00 95.05 0.00 98.24 0.00 95.08 0.00 97.85 0.00 94.68 0.00 90.71 1.57 /workspace/coverage/default/33.spi_device_flash_all.1944936966
96.00 0.19 99.06 0.00 95.98 0.93 98.24 0.00 95.08 0.00 97.87 0.02 94.68 0.00 91.09 0.38 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2757133143
96.17 0.17 99.06 0.00 95.98 0.00 98.24 0.00 95.08 0.00 97.87 0.00 94.68 0.00 92.28 1.19 /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3717709475
96.32 0.15 99.06 0.00 95.98 0.00 98.24 0.00 95.08 0.00 97.87 0.00 94.68 0.00 93.33 1.05 /workspace/coverage/default/31.spi_device_flash_and_tpm.3419096418
96.45 0.13 99.06 0.00 95.98 0.00 98.24 0.00 95.08 0.00 97.87 0.00 95.57 0.89 93.33 0.00 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.519753307
96.57 0.12 99.06 0.00 95.98 0.00 98.24 0.00 95.08 0.00 97.87 0.00 95.57 0.00 94.19 0.86 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2814073694
96.69 0.12 99.06 0.00 95.98 0.00 98.24 0.00 95.08 0.00 97.87 0.00 95.57 0.00 95.05 0.86 /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.24068226
96.80 0.11 99.06 0.00 95.98 0.00 98.24 0.00 95.08 0.00 97.87 0.00 95.57 0.00 95.81 0.76 /workspace/coverage/default/34.spi_device_stress_all.1867163817
96.88 0.07 99.06 0.00 95.98 0.00 98.24 0.00 95.08 0.00 97.87 0.00 95.57 0.00 96.33 0.52 /workspace/coverage/default/5.spi_device_flash_and_tpm.3818417109
96.94 0.07 99.06 0.00 95.98 0.00 98.24 0.00 95.08 0.00 97.87 0.00 95.57 0.00 96.81 0.48 /workspace/coverage/default/9.spi_device_flash_all.288765350
97.01 0.07 99.06 0.00 96.00 0.03 98.43 0.20 95.08 0.00 97.87 0.00 95.72 0.15 96.90 0.10 /workspace/coverage/default/0.spi_device_sec_cm.1233758142
97.07 0.06 99.06 0.00 96.08 0.08 98.43 0.00 95.08 0.00 97.90 0.03 95.72 0.00 97.24 0.33 /workspace/coverage/default/37.spi_device_stress_all.1597926451
97.12 0.04 99.07 0.01 96.08 0.00 98.43 0.00 95.08 0.00 97.92 0.02 95.72 0.00 97.52 0.29 /workspace/coverage/default/18.spi_device_flash_and_tpm.154840537
97.16 0.04 99.10 0.03 96.08 0.00 98.43 0.00 95.08 0.00 97.93 0.02 95.86 0.15 97.62 0.10 /workspace/coverage/default/30.spi_device_stress_all.1677183437
97.20 0.04 99.10 0.00 96.08 0.00 98.43 0.00 95.08 0.00 97.93 0.00 95.86 0.00 97.90 0.29 /workspace/coverage/default/36.spi_device_flash_all.1849407036
97.23 0.03 99.16 0.06 96.17 0.09 98.43 0.00 95.08 0.00 98.02 0.08 95.86 0.00 97.90 0.00 /workspace/coverage/default/0.spi_device_mem_parity.890558403
97.26 0.03 99.16 0.00 96.19 0.03 98.63 0.20 95.08 0.00 98.02 0.00 95.86 0.00 97.90 0.00 /workspace/coverage/default/14.spi_device_alert_test.1089629423
97.29 0.03 99.16 0.00 96.19 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.09 0.19 /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2941509705
97.32 0.02 99.16 0.00 96.22 0.03 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.24 0.14 /workspace/coverage/default/34.spi_device_bit_transfer.1695334974
97.34 0.02 99.16 0.00 96.22 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.38 0.14 /workspace/coverage/default/13.spi_device_flash_mode.1841908109
97.36 0.02 99.16 0.00 96.22 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.52 0.14 /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.559561860
97.37 0.02 99.16 0.00 96.23 0.01 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.62 0.10 /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3344823694
97.39 0.01 99.16 0.00 96.23 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.71 0.10 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2262412595
97.40 0.01 99.16 0.00 96.23 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.81 0.10 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2897055245
97.41 0.01 99.16 0.00 96.23 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 98.90 0.10 /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.962139991
97.43 0.01 99.16 0.00 96.23 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.00 0.10 /workspace/coverage/default/22.spi_device_flash_all.1288962571
97.44 0.01 99.16 0.00 96.23 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.09 0.10 /workspace/coverage/default/24.spi_device_flash_and_tpm.47293567
97.45 0.01 99.16 0.00 96.23 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.19 0.10 /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2699400736
97.47 0.01 99.16 0.00 96.23 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.29 0.10 /workspace/coverage/default/34.spi_device_flash_and_tpm.4259668130
97.48 0.01 99.16 0.00 96.23 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.38 0.10 /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1844635277
97.49 0.01 99.16 0.00 96.24 0.01 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.43 0.05 /workspace/coverage/default/21.spi_device_fifo_underflow_overflow.1263579956
97.50 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.48 0.05 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.836570122
97.50 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.52 0.05 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2516926122
97.51 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.57 0.05 /workspace/coverage/default/10.spi_device_fifo_underflow_overflow.45654408
97.52 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.62 0.05 /workspace/coverage/default/10.spi_device_flash_and_tpm.4097876591
97.52 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.67 0.05 /workspace/coverage/default/17.spi_device_intr.3692414877
97.53 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.71 0.05 /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3420241680
97.54 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.76 0.05 /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1721280745
97.54 0.01 99.17 0.01 96.26 0.01 98.63 0.00 95.08 0.00 98.04 0.02 95.86 0.00 99.76 0.00 /workspace/coverage/default/10.spi_device_mailbox.1265909563
97.55 0.01 99.18 0.01 96.27 0.01 98.63 0.00 95.08 0.00 98.05 0.02 95.86 0.00 99.76 0.00 /workspace/coverage/default/3.spi_device_abort.588053541
97.55 0.01 99.18 0.00 96.30 0.03 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2767762995
97.55 0.01 99.18 0.00 96.31 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/13.spi_device_rx_async_fifo_reset.1867883466
97.56 0.01 99.18 0.00 96.32 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/16.spi_device_tx_async_fifo_reset.1676329511
97.56 0.01 99.18 0.00 96.33 0.01 98.63 0.00 95.08 0.00 98.05 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/21.spi_device_flash_and_tpm.2716790834

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1402742148
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3371081391
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3352885678
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3749668432
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3797739973
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3710452745
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.414139656
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3728776524
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.981683214
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.375316379
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.917494483
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1307782600
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2408918364
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.719638226
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2183786873
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3568792795
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3309144469
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2786719384
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4250025232
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3446934011
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.1774482943
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.912949301
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1325279719
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1843198387
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3052213110
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.677947774
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4040394235
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3548981429
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1198953062
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3307517334
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2873595661
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.3681954945
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3621031096
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3559626663
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.992995605
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1142249924
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1460139496
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1281489727
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3288825874
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2568121808
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3861009420
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1026173171
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3298036816
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.3310957750
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2717805602
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1867587003
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.478345202
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.410524607
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.3520472976
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3417621884
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2128406323
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3225229471
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3654491636
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1508570168
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.3419647183
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2815027737
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3203708582
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1408331828
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2845970148
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.408538576
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.3874371859
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.174565651
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3379462878
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1679497781
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2812086636
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3766482769
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.1267508888
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2487807757
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1327169233
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2133390489
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.588040379
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2298901439
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.89390614
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.510194544
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3555110484
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.929065390
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2083993557
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1267137676
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2753441695
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1210614485
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.855020486
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.973774540
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.208530473
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1505288858
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2402336298
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3791219802
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.2210089200
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.773149894
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.423669673
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.59276291
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.2417734105
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.1714336444
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.4086034643
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.1107869983
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.2445728480
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.440052235
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3466765533
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3343742125
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2706433073
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3218246788
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.960984307
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.3393358925
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.149691756
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3347993391
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.369305383
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.232592557
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1189101970
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.3184094398
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.549746739
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.180505277
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.1552214530
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.1014114642
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.2279510928
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.1016897984
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.387510196
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3299031234
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/workspace/coverage/default/7.spi_device_flash_mode.3825768555
/workspace/coverage/default/7.spi_device_intercept.2981014281
/workspace/coverage/default/7.spi_device_intr.851177480
/workspace/coverage/default/7.spi_device_mailbox.402594513
/workspace/coverage/default/7.spi_device_mem_parity.167859194
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3190350618
/workspace/coverage/default/7.spi_device_pass_cmd_filtering.3351895016
/workspace/coverage/default/7.spi_device_perf.2668107242
/workspace/coverage/default/7.spi_device_ram_cfg.703553141
/workspace/coverage/default/7.spi_device_read_buffer_direct.2156557187
/workspace/coverage/default/7.spi_device_rx_async_fifo_reset.487714386
/workspace/coverage/default/7.spi_device_rx_timeout.4233837588
/workspace/coverage/default/7.spi_device_smoke.828213796
/workspace/coverage/default/7.spi_device_stress_all.3412983773
/workspace/coverage/default/7.spi_device_tpm_all.489598161
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1813322950
/workspace/coverage/default/7.spi_device_tpm_rw.470104534
/workspace/coverage/default/7.spi_device_tpm_sts_read.3781450244
/workspace/coverage/default/7.spi_device_tx_async_fifo_reset.2878281135
/workspace/coverage/default/7.spi_device_txrx.560956646
/workspace/coverage/default/7.spi_device_upload.37908165
/workspace/coverage/default/8.spi_device_abort.2764109917
/workspace/coverage/default/8.spi_device_alert_test.1932255443
/workspace/coverage/default/8.spi_device_bit_transfer.3781143594
/workspace/coverage/default/8.spi_device_byte_transfer.267356670
/workspace/coverage/default/8.spi_device_cfg_cmd.2241637071
/workspace/coverage/default/8.spi_device_csb_read.2879340307
/workspace/coverage/default/8.spi_device_dummy_item_extra_dly.4088576334
/workspace/coverage/default/8.spi_device_extreme_fifo_size.901030036
/workspace/coverage/default/8.spi_device_fifo_full.1441608517
/workspace/coverage/default/8.spi_device_fifo_underflow_overflow.4005826052
/workspace/coverage/default/8.spi_device_flash_all.687380793
/workspace/coverage/default/8.spi_device_flash_and_tpm.3086152378
/workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2067872123
/workspace/coverage/default/8.spi_device_flash_mode.1065885824
/workspace/coverage/default/8.spi_device_intercept.1166777372
/workspace/coverage/default/8.spi_device_intr.1211084773
/workspace/coverage/default/8.spi_device_mailbox.4166593172
/workspace/coverage/default/8.spi_device_mem_parity.1788018618
/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1646167924
/workspace/coverage/default/8.spi_device_pass_cmd_filtering.228351235
/workspace/coverage/default/8.spi_device_perf.1621192896
/workspace/coverage/default/8.spi_device_ram_cfg.1963907747
/workspace/coverage/default/8.spi_device_read_buffer_direct.1747981386
/workspace/coverage/default/8.spi_device_rx_async_fifo_reset.1263522243
/workspace/coverage/default/8.spi_device_rx_timeout.1780359689
/workspace/coverage/default/8.spi_device_smoke.465414371
/workspace/coverage/default/8.spi_device_stress_all.1688166295
/workspace/coverage/default/8.spi_device_tpm_all.1034170042
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2222538900
/workspace/coverage/default/8.spi_device_tpm_rw.4043978365
/workspace/coverage/default/8.spi_device_tpm_sts_read.153714908
/workspace/coverage/default/8.spi_device_tx_async_fifo_reset.1014126094
/workspace/coverage/default/8.spi_device_txrx.3286664304
/workspace/coverage/default/8.spi_device_upload.2049943608
/workspace/coverage/default/9.spi_device_abort.517923540
/workspace/coverage/default/9.spi_device_alert_test.2932639563
/workspace/coverage/default/9.spi_device_bit_transfer.51262782
/workspace/coverage/default/9.spi_device_byte_transfer.2063219186
/workspace/coverage/default/9.spi_device_cfg_cmd.3979466368
/workspace/coverage/default/9.spi_device_csb_read.1359266805
/workspace/coverage/default/9.spi_device_dummy_item_extra_dly.1582164681
/workspace/coverage/default/9.spi_device_extreme_fifo_size.919036064
/workspace/coverage/default/9.spi_device_fifo_full.2395066768
/workspace/coverage/default/9.spi_device_fifo_underflow_overflow.4087507870
/workspace/coverage/default/9.spi_device_flash_and_tpm.3719009000
/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3726974454
/workspace/coverage/default/9.spi_device_flash_mode.2662164312
/workspace/coverage/default/9.spi_device_intercept.666518633
/workspace/coverage/default/9.spi_device_intr.595462697
/workspace/coverage/default/9.spi_device_mailbox.1767560528
/workspace/coverage/default/9.spi_device_mem_parity.3938234911
/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.418687832
/workspace/coverage/default/9.spi_device_pass_cmd_filtering.202051578
/workspace/coverage/default/9.spi_device_perf.1850217344
/workspace/coverage/default/9.spi_device_ram_cfg.3751409922
/workspace/coverage/default/9.spi_device_read_buffer_direct.315024330
/workspace/coverage/default/9.spi_device_rx_async_fifo_reset.2877001285
/workspace/coverage/default/9.spi_device_rx_timeout.4207127945
/workspace/coverage/default/9.spi_device_smoke.4210259077
/workspace/coverage/default/9.spi_device_stress_all.1227332378
/workspace/coverage/default/9.spi_device_tpm_all.3202877618
/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3787533749
/workspace/coverage/default/9.spi_device_tpm_rw.2380526666
/workspace/coverage/default/9.spi_device_tpm_sts_read.3793428239
/workspace/coverage/default/9.spi_device_tx_async_fifo_reset.520115814
/workspace/coverage/default/9.spi_device_txrx.3746216283
/workspace/coverage/default/9.spi_device_upload.2442686349



Total test records in report: 1786
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/10.spi_device_mailbox.1265909563 Dec 31 01:08:52 PM PST 23 Dec 31 01:09:26 PM PST 23 9311396157 ps
T1 /workspace/coverage/default/28.spi_device_extreme_fifo_size.4016686903 Dec 31 01:10:22 PM PST 23 Dec 31 01:10:51 PM PST 23 5523953366 ps
T5 /workspace/coverage/default/28.spi_device_alert_test.2340248547 Dec 31 01:10:17 PM PST 23 Dec 31 01:10:24 PM PST 23 12602500 ps
T2 /workspace/coverage/default/29.spi_device_rx_async_fifo_reset.1936236030 Dec 31 01:10:16 PM PST 23 Dec 31 01:10:23 PM PST 23 22902830 ps
T10 /workspace/coverage/default/46.spi_device_mailbox.1096008805 Dec 31 01:12:22 PM PST 23 Dec 31 01:12:39 PM PST 23 794482874 ps
T3 /workspace/coverage/default/34.spi_device_bit_transfer.1695334974 Dec 31 01:10:53 PM PST 23 Dec 31 01:10:58 PM PST 23 572769488 ps
T27 /workspace/coverage/default/8.spi_device_csb_read.2879340307 Dec 31 01:08:47 PM PST 23 Dec 31 01:08:49 PM PST 23 35003352 ps
T6 /workspace/coverage/default/34.spi_device_flash_all.4276937126 Dec 31 01:10:54 PM PST 23 Dec 31 01:13:01 PM PST 23 48233870507 ps
T11 /workspace/coverage/default/15.spi_device_extreme_fifo_size.1230083371 Dec 31 01:09:11 PM PST 23 Dec 31 01:51:49 PM PST 23 69539084161 ps
T7 /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1413006458 Dec 31 01:09:39 PM PST 23 Dec 31 01:16:31 PM PST 23 69695710692 ps
T12 /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4119087285 Dec 31 01:11:44 PM PST 23 Dec 31 01:12:16 PM PST 23 69428191473 ps
T13 /workspace/coverage/default/45.spi_device_tpm_all.3191937644 Dec 31 01:12:19 PM PST 23 Dec 31 01:12:35 PM PST 23 9200088609 ps
T61 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2402336298 Dec 31 12:48:58 PM PST 23 Dec 31 12:49:02 PM PST 23 292790723 ps
T57 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.180505277 Dec 31 12:49:15 PM PST 23 Dec 31 12:49:18 PM PST 23 43866414 ps
T71 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1048755363 Dec 31 12:49:23 PM PST 23 Dec 31 12:49:46 PM PST 23 885780376 ps
T58 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2176867611 Dec 31 12:49:48 PM PST 23 Dec 31 12:49:49 PM PST 23 16420780 ps
T134 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4040394235 Dec 31 12:49:26 PM PST 23 Dec 31 12:49:32 PM PST 23 3510395309 ps
T59 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3520472976 Dec 31 12:49:27 PM PST 23 Dec 31 12:49:29 PM PST 23 10904699 ps
T72 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1189101970 Dec 31 12:48:52 PM PST 23 Dec 31 12:49:10 PM PST 23 1153703668 ps
T135 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3298036816 Dec 31 12:49:02 PM PST 23 Dec 31 12:49:05 PM PST 23 33021086 ps
T136 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3446934011 Dec 31 12:49:05 PM PST 23 Dec 31 12:49:09 PM PST 23 263559252 ps
T137 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2408918364 Dec 31 12:49:54 PM PST 23 Dec 31 12:49:59 PM PST 23 40856732 ps
T138 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3797739973 Dec 31 12:49:05 PM PST 23 Dec 31 12:49:09 PM PST 23 201047232 ps
T56 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1916099983 Dec 31 12:49:12 PM PST 23 Dec 31 12:49:16 PM PST 23 223398453 ps
T108 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2266602986 Dec 31 12:49:01 PM PST 23 Dec 31 12:49:04 PM PST 23 195431550 ps
T109 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3379462878 Dec 31 12:49:15 PM PST 23 Dec 31 12:49:19 PM PST 23 85509831 ps
T126 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3766482769 Dec 31 12:49:15 PM PST 23 Dec 31 12:49:18 PM PST 23 92041906 ps
T127 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1267137676 Dec 31 12:49:27 PM PST 23 Dec 31 12:50:04 PM PST 23 2311137969 ps
T110 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3203708582 Dec 31 12:49:21 PM PST 23 Dec 31 12:49:24 PM PST 23 254654934 ps
T60 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.51060615 Dec 31 12:48:58 PM PST 23 Dec 31 12:49:00 PM PST 23 14645686 ps
T128 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1982926651 Dec 31 12:48:49 PM PST 23 Dec 31 12:48:52 PM PST 23 67809370 ps
T129 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3307517334 Dec 31 12:49:05 PM PST 23 Dec 31 12:49:09 PM PST 23 135688488 ps
T130 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2814073694 Dec 31 12:49:26 PM PST 23 Dec 31 12:49:28 PM PST 23 166340993 ps
T133 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3052213110 Dec 31 12:49:16 PM PST 23 Dec 31 12:49:20 PM PST 23 38424918 ps
T113 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.268520456 Dec 31 12:49:21 PM PST 23 Dec 31 12:49:27 PM PST 23 134117871 ps
T117 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2706433073 Dec 31 12:48:49 PM PST 23 Dec 31 12:48:51 PM PST 23 14781136 ps
T186 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2246005756 Dec 31 12:49:17 PM PST 23 Dec 31 12:49:19 PM PST 23 122361972 ps
T187 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2801802467 Dec 31 12:49:20 PM PST 23 Dec 31 12:49:22 PM PST 23 13637404 ps
T114 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2757133143 Dec 31 12:49:19 PM PST 23 Dec 31 12:49:24 PM PST 23 96608308 ps
T188 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1016897984 Dec 31 12:49:17 PM PST 23 Dec 31 12:49:19 PM PST 23 50210653 ps
T170 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.773149894 Dec 31 12:49:14 PM PST 23 Dec 31 12:49:16 PM PST 23 16316130 ps
T112 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.523111523 Dec 31 12:49:15 PM PST 23 Dec 31 12:49:37 PM PST 23 2062980532 ps
T115 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1867587003 Dec 31 12:49:18 PM PST 23 Dec 31 12:49:22 PM PST 23 33156093 ps
T158 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3510659489 Dec 31 12:49:28 PM PST 23 Dec 31 12:49:31 PM PST 23 165242485 ps
T159 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.588040379 Dec 31 12:49:14 PM PST 23 Dec 31 12:49:17 PM PST 23 46050274 ps
T166 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.440052235 Dec 31 12:49:09 PM PST 23 Dec 31 12:49:11 PM PST 23 29099425 ps
T167 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1516288827 Dec 31 12:49:00 PM PST 23 Dec 31 12:49:03 PM PST 23 110752168 ps
T168 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3417621884 Dec 31 12:49:29 PM PST 23 Dec 31 12:49:34 PM PST 23 132142351 ps
T169 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.174565651 Dec 31 12:49:28 PM PST 23 Dec 31 12:49:32 PM PST 23 54574427 ps
T139 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.208530473 Dec 31 12:49:17 PM PST 23 Dec 31 12:49:23 PM PST 23 139280379 ps
T335 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3568792795 Dec 31 12:49:03 PM PST 23 Dec 31 12:49:09 PM PST 23 4091532686 ps
T336 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.478345202 Dec 31 12:49:23 PM PST 23 Dec 31 12:49:26 PM PST 23 32216627 ps
T171 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2262412595 Dec 31 12:48:42 PM PST 23 Dec 31 12:48:45 PM PST 23 14677268 ps
T116 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2250390387 Dec 31 12:49:25 PM PST 23 Dec 31 12:49:29 PM PST 23 762004941 ps
T337 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3218246788 Dec 31 12:49:24 PM PST 23 Dec 31 12:49:28 PM PST 23 39971162 ps
T172 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2211333226 Dec 31 12:49:13 PM PST 23 Dec 31 12:49:15 PM PST 23 45798249 ps
T338 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.59276291 Dec 31 12:49:21 PM PST 23 Dec 31 12:49:24 PM PST 23 17542807 ps
T125 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2767762995 Dec 31 12:49:31 PM PST 23 Dec 31 12:49:38 PM PST 23 388770850 ps
T140 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.519753307 Dec 31 12:49:08 PM PST 23 Dec 31 12:49:12 PM PST 23 175572224 ps
T339 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1505288858 Dec 31 12:49:13 PM PST 23 Dec 31 12:49:25 PM PST 23 685923946 ps
T131 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3555110484 Dec 31 12:49:21 PM PST 23 Dec 31 12:49:30 PM PST 23 66247464 ps
T340 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2832378736 Dec 31 12:48:58 PM PST 23 Dec 31 12:49:00 PM PST 23 84172616 ps
T132 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1358129087 Dec 31 12:49:26 PM PST 23 Dec 31 12:49:34 PM PST 23 502654804 ps
T341 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1402742148 Dec 31 12:48:47 PM PST 23 Dec 31 12:48:57 PM PST 23 1493179122 ps
T342 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3347993391 Dec 31 12:49:02 PM PST 23 Dec 31 12:49:12 PM PST 23 856566936 ps
T343 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1464235707 Dec 31 12:48:51 PM PST 23 Dec 31 12:48:54 PM PST 23 43124699 ps
T344 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3559626663 Dec 31 12:49:14 PM PST 23 Dec 31 12:49:17 PM PST 23 88935079 ps
T345 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1348440464 Dec 31 12:49:07 PM PST 23 Dec 31 12:49:09 PM PST 23 16228348 ps
T141 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1508570168 Dec 31 12:49:26 PM PST 23 Dec 31 12:49:29 PM PST 23 124233242 ps
T142 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.446936160 Dec 31 12:49:41 PM PST 23 Dec 31 12:49:45 PM PST 23 499429174 ps
T346 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2568121808 Dec 31 12:49:18 PM PST 23 Dec 31 12:49:22 PM PST 23 84929067 ps
T347 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4086034643 Dec 31 12:49:25 PM PST 23 Dec 31 12:49:27 PM PST 23 25353831 ps
T160 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2133390489 Dec 31 12:49:01 PM PST 23 Dec 31 12:49:18 PM PST 23 750521162 ps
T198 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.330339649 Dec 31 12:49:19 PM PST 23 Dec 31 12:49:41 PM PST 23 359993134 ps
T348 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1843198387 Dec 31 12:49:23 PM PST 23 Dec 31 12:49:27 PM PST 23 96249338 ps
T161 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1210614485 Dec 31 12:48:55 PM PST 23 Dec 31 12:48:58 PM PST 23 87389538 ps
T162 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2626513893 Dec 31 12:48:47 PM PST 23 Dec 31 12:48:52 PM PST 23 174934312 ps
T349 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.917494483 Dec 31 12:49:17 PM PST 23 Dec 31 12:49:33 PM PST 23 2791709268 ps
T350 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2254996637 Dec 31 12:49:46 PM PST 23 Dec 31 12:49:48 PM PST 23 43272080 ps
T163 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1198953062 Dec 31 12:49:15 PM PST 23 Dec 31 12:49:24 PM PST 23 2594943032 ps
T351 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1458871861 Dec 31 12:48:45 PM PST 23 Dec 31 12:48:49 PM PST 23 41042766 ps
T352 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.888167030 Dec 31 12:49:25 PM PST 23 Dec 31 12:49:27 PM PST 23 14634973 ps
T353 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1714336444 Dec 31 12:49:33 PM PST 23 Dec 31 12:49:36 PM PST 23 28856992 ps
T143 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.410524607 Dec 31 12:49:10 PM PST 23 Dec 31 12:49:13 PM PST 23 70390962 ps
T354 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2845970148 Dec 31 12:49:21 PM PST 23 Dec 31 12:49:24 PM PST 23 89568527 ps
T355 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3681954945 Dec 31 12:49:18 PM PST 23 Dec 31 12:49:20 PM PST 23 17796798 ps
T356 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.232592557 Dec 31 12:49:10 PM PST 23 Dec 31 12:49:16 PM PST 23 145715825 ps
T357 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.973774540 Dec 31 12:49:01 PM PST 23 Dec 31 12:49:02 PM PST 23 10762225 ps
T358 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1723833242 Dec 31 12:48:57 PM PST 23 Dec 31 12:49:05 PM PST 23 122708729 ps
T359 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1157623294 Dec 31 12:49:33 PM PST 23 Dec 31 12:49:40 PM PST 23 138684742 ps
T200 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2786719384 Dec 31 12:49:11 PM PST 23 Dec 31 12:49:20 PM PST 23 278413509 ps
T360 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1844831589 Dec 31 12:49:08 PM PST 23 Dec 31 12:49:11 PM PST 23 105022949 ps
T144 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3299031234 Dec 31 12:49:30 PM PST 23 Dec 31 12:49:40 PM PST 23 433973285 ps
T361 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3791219802 Dec 31 12:49:01 PM PST 23 Dec 31 12:49:06 PM PST 23 104882369 ps
T362 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3654491636 Dec 31 12:49:08 PM PST 23 Dec 31 12:49:10 PM PST 23 39513011 ps
T363 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2438026596 Dec 31 12:49:21 PM PST 23 Dec 31 12:49:22 PM PST 23 19517490 ps
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T448 /workspace/coverage/default/46.spi_device_dummy_item_extra_dly.4048431495 Dec 31 01:12:15 PM PST 23 Dec 31 01:20:40 PM PST 23 321954944322 ps
T91 /workspace/coverage/default/18.spi_device_tpm_all.2288236333 Dec 31 01:09:39 PM PST 23 Dec 31 01:10:22 PM PST 23 10264626352 ps
T74 /workspace/coverage/default/0.spi_device_ram_cfg.3395319302 Dec 31 01:07:31 PM PST 23 Dec 31 01:07:33 PM PST 23 20063115 ps
T449 /workspace/coverage/default/47.spi_device_alert_test.3256224605 Dec 31 01:12:20 PM PST 23 Dec 31 01:12:26 PM PST 23 34432359 ps
T250 /workspace/coverage/default/36.spi_device_pass_cmd_filtering.62416413 Dec 31 01:11:18 PM PST 23 Dec 31 01:11:33 PM PST 23 1940313442 ps
T106 /workspace/coverage/default/22.spi_device_fifo_underflow_overflow.727487240 Dec 31 01:09:59 PM PST 23 Dec 31 01:13:06 PM PST 23 183927144794 ps
T68 /workspace/coverage/default/22.spi_device_rx_async_fifo_reset.3134768475 Dec 31 01:10:18 PM PST 23 Dec 31 01:10:27 PM PST 23 125748565 ps
T93 /workspace/coverage/default/18.spi_device_flash_and_tpm.154840537 Dec 31 01:09:39 PM PST 23 Dec 31 01:10:32 PM PST 23 11242451575 ps
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T42 /workspace/coverage/default/39.spi_device_fifo_underflow_overflow.614963166 Dec 31 01:11:19 PM PST 23 Dec 31 01:19:49 PM PST 23 282670820392 ps
T20 /workspace/coverage/default/0.spi_device_flash_all.2802603181 Dec 31 01:08:04 PM PST 23 Dec 31 01:08:45 PM PST 23 21062498445 ps
T265 /workspace/coverage/default/32.spi_device_upload.2341811639 Dec 31 01:10:52 PM PST 23 Dec 31 01:11:06 PM PST 23 2601751789 ps
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