Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

Group : spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	16	0	16	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_bit_order	2	0	2	100.00	100	1	1	2
cp_cpha	2	0	2	100.00	100	1	1	2
cp_cpol	2	0	2	100.00	100	1	1	2
cp_rx_order	2	0	2	100.00	100	1	1	2
rx_order	2	0	2	100.00	100	1	1	2
tx_order	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_bit_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bit_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3689528

1

T3

45

T11

2928

T8

9101

auto[1]

3440728

1

T1

1534

T2

12

T3

36

---

Summary for Variable cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpha

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3792233

1

T1

678

T3

62

T11

888

auto[1]

3338023

1

T1

856

T2

12

T3

19

---

Summary for Variable cp_cpol

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpol

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3718197

1

T1

678

T3

23

T11

888

auto[1]

3412059

1

T1

856

T2

12

T3

58

---

Summary for Variable cp_rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3768704

1

T1

856

T2

12

T3

57

auto[1]

3361552

1

T1

678

T3

24

T11

2040

---

Summary for Variable rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3768704

1

T1

856

T2

12

T3

57

auto[1]

3361552

1

T1

678

T3

24

T11

2040

---

Summary for Variable tx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for tx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3689528

1

T3

45

T11

2928

T8

9101

auto[1]

3440728

1

T1

1534

T2

12

T3

36

---

Summary for Cross cr_all

Samples crossed: tx_order rx_order cp_cpol cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

tx_order

rx_order

cp_cpol

cp_cpha

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

426700

1

T3

6

T11

888

T23

744

auto[0]

auto[0]

auto[0]

auto[1]

552548

1

T49

1

T50

9

T180

5941

auto[0]

auto[0]

auto[1]

auto[0]

552062

1

T3

23

T50

7

T40

1924

auto[0]

auto[0]

auto[1]

auto[1]

430243

1

T8

2906

T25

148

T202

8

auto[0]

auto[1]

auto[0]

auto[0]

523435

1

T8

6195

T50

8

T179

8311

auto[0]

auto[1]

auto[0]

auto[1]

400712

1

T3

1

T39

6068

T202

11

auto[0]

auto[1]

auto[1]

auto[0]

432162

1

T3

13

T38

784

T48

8865

auto[0]

auto[1]

auto[1]

auto[1]

371666

1

T3

2

T11

2040

T23

818

auto[1]

auto[0]

auto[0]

auto[0]

555941

1

T3

6

T50

6

T179

7608

auto[1]

auto[0]

auto[0]

auto[1]

409517

1

T3

6

T8

7546

T41

5507

auto[1]

auto[0]

auto[1]

auto[0]

346980

1

T3

10

T26

564

T37

1

auto[1]

auto[0]

auto[1]

auto[1]

494713

1

T1

856

T2

12

T3

6

auto[1]

auto[1]

auto[0]

auto[0]

507774

1

T1

678

T3

4

T8

23183

auto[1]

auto[1]

auto[0]

auto[1]

341570

1

T23

5232

T50

6

T203

10

auto[1]

auto[1]

auto[1]

auto[0]

447179

1

T33

12

T41

4528

T54

1335

auto[1]

auto[1]

auto[1]

auto[1]

337054

1

T3

4

T23

8042

T50

8