Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35794	1			T4	14		T10	18		T6	532
auto[SpiFlashAddrCfg]	7532	1			T6	65		T7	89		T12	2
auto[SpiFlashAddr3b]	9141	1			T6	55		T7	107		T12	4
auto[SpiFlashAddr4b]	7727	1			T6	67		T7	72		T12	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33425

1

T4

14

T10

18

T6

396

auto[1]

26769

1

T6

323

T7

246

T8

30

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32036

1

T4

4

T10

8

T6

567

auto[1]

28158

1

T4

10

T10

10

T6

152

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40333	1			T4	14		T10	18		T6	575
values[1]	1110	1			T6	5		T7	13		T8	1
values[2]	1448	1			T6	16		T7	15		T23	10
values[3]	1427	1			T6	6		T7	21		T8	1
values[4]	1389	1			T6	12		T7	24		T12	2
values[5]	1462	1			T6	3		T7	16		T23	7
values[6]	1554	1			T6	11		T7	15		T8	2
values[7]	1535	1			T6	12		T7	18		T12	2
values[8]	9936	1			T6	79		T7	94		T12	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32948

1

T4

14

T10

18

T6

719

auto[1]

27246

1

T23

172

T32

15

T29

208

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58165

1

T4

14

T10

18

T6

695

write

2029

1

T6

24

T7

14

T8

3

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19873

1

T6

129

T7

211

T12

4

valids[0x1]

40321

1

T4

14

T10

18

T6

590

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1604	1			T4	2		T10	2		T6	10
internal_process_ops[0x5a]	1562	1			T6	10		T7	12		T12	2
internal_process_ops[0x05]	21971	1			T10	2		T6	431		T7	223
internal_process_ops[0x35]	1532	1			T4	4		T10	8		T6	13
internal_process_ops[0x15]	1550	1			T4	8		T10	6		T6	17
internal_process_ops[0x03]	1204	1			T6	8		T7	14		T12	4
internal_process_ops[0x0b]	1138	1			T6	12		T7	14		T8	1
internal_process_ops[0x3b]	1109	1			T6	4		T7	9		T8	1
internal_process_ops[0x6b]	1138	1			T6	7		T7	13		T8	1
internal_process_ops[0xbb]	1166	1			T6	7		T7	8		T8	1
internal_process_ops[0xeb]	1161	1			T6	9		T7	16		T8	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59188

1

T4

14

T10

18

T6

715

auto[1]

1006

1

T6

4

T7

6

T8

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58227

1

T4

14

T10

18

T6

699

auto[1]

1967

1

T6

20

T7

23

T8

1

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11049

1

T4

14

T10

18

T6

311

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7569

1

T6

216

T7

118

T8

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2066

1

T6

32

T7

45

T12

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1833

1

T6

28

T7

42

T8

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2797

1

T6

18

T7

58

T12

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2308

1

T6

34

T7

44

T8

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2259

1

T6

23

T7

31

T12

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1988

1

T6

33

T7

35

T8

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

76

1

T6

4

T19

2

T20

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

66

1

T7

1

T18

1

T19

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

67

1

T19

3

T22

2

T175

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

74

1

T6

1

T18

1

T100

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

97

1

T6

1

T7

2

T14

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

65

1

T14

2

T15

1

T19

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

64

1

T6

4

T14

1

T16

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

77

1

T18

1

T19

1

T21

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

70

1

T7

2

T18

5

T19

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

58

1

T6

3

T8

1

T14

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

41

1

T7

3

T14

2

T18

5

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

56

1

T14

4

T20

1

T100

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

83

1

T6

4

T7

1

T16

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

48

1

T7

1

T8

1

T14

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

60

1

T6

7

T16

1

T19

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

77

1

T7

4

T8

1

T19

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9022

1

T23

50

T29

62

T93

8

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7619

1

T23

37

T29

91

T93

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1701

1

T23

16

T32

6

T29

6

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1398

1

T23

12

T29

8

T30

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1905

1

T23

15

T29

7

T151

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1680

1

T23

8

T29

8

T93

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1579

1

T23

18

T32

9

T29

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1392

1

T23

8

T29

6

T93

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

56

1

T23

3

T189

1

T190

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

53

1

T191

3

T192

1

T193

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

73

1

T23

2

T30

3

T62

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

70

1

T189

1

T190

5

T62

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

62

1

T30

1

T189

1

T190

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

75

1

T191

2

T193

3

T62

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

36

1

T30

2

T191

1

T190

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

58

1

T29

1

T190

5

T194

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

64

1

T30

1

T189

1

T190

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

44

1

T30

1

T190

3

T193

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

64

1

T29

2

T30

2

T190

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

54

1

T192

3

T190

3

T195

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

59

1

T23

1

T30

1

T192

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

71

1

T23

2

T192

2

T194

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

51

1

T193

4

T62

1

T195

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

60

1

T29

2

T30

1

T190

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4266	1			T6	52		T7	85		T8	6
auto[0]	values[0]	valids[0x1]	17081	1			T4	14		T10	18		T6	523
auto[0]	values[1]	valids[0x1]	613	1			T6	5		T7	13		T8	1
auto[0]	values[2]	valids[0x0]	572	1			T6	12		T7	12		T14	5
auto[0]	values[2]	valids[0x1]	304	1			T6	4		T7	3		T14	2
auto[0]	values[3]	valids[0x0]	505	1			T6	5		T7	6		T14	7
auto[0]	values[3]	valids[0x1]	345	1			T6	1		T7	15		T8	1
auto[0]	values[4]	valids[0x0]	534	1			T6	7		T7	21		T8	3
auto[0]	values[4]	valids[0x1]	287	1			T6	5		T7	3		T12	2
auto[0]	values[5]	valids[0x0]	610	1			T6	2		T7	11		T14	13
auto[0]	values[5]	valids[0x1]	270	1			T6	1		T7	5		T16	1
auto[0]	values[6]	valids[0x0]	545	1			T6	5		T7	8		T14	8
auto[0]	values[6]	valids[0x1]	372	1			T6	6		T7	7		T8	2
auto[0]	values[7]	valids[0x0]	554	1			T6	7		T7	9		T12	2
auto[0]	values[7]	valids[0x1]	341	1			T6	5		T7	9		T14	6
auto[0]	values[8]	valids[0x0]	3624	1			T6	39		T7	59		T12	2
auto[0]	values[8]	valids[0x1]	2125	1			T6	40		T7	35		T12	2
auto[1]	values[0]	valids[0x0]	3998	1			T23	31		T29	28		T93	5
auto[1]	values[0]	valids[0x1]	14988	1			T23	68		T29	146		T93	4
auto[1]	values[1]	valids[0x1]	497	1			T23	5		T29	3		T30	8
auto[1]	values[2]	valids[0x0]	323	1			T23	3		T93	1		T30	8
auto[1]	values[2]	valids[0x1]	249	1			T23	7		T30	1		T191	2
auto[1]	values[3]	valids[0x0]	347	1			T23	3		T29	2		T154	5
auto[1]	values[3]	valids[0x1]	230	1			T23	5		T93	2		T30	6
auto[1]	values[4]	valids[0x0]	370	1			T23	2		T154	12		T30	1
auto[1]	values[4]	valids[0x1]	198	1			T23	1		T30	2		T191	1
auto[1]	values[5]	valids[0x0]	366	1			T23	7		T29	3		T30	6
auto[1]	values[5]	valids[0x1]	216	1			T29	4		T93	3		T30	2
auto[1]	values[6]	valids[0x0]	404	1			T23	5		T29	2		T151	4
auto[1]	values[6]	valids[0x1]	233	1			T23	1		T29	1		T30	2
auto[1]	values[7]	valids[0x0]	383	1			T23	2		T29	1		T151	2
auto[1]	values[7]	valids[0x1]	257	1			T23	2		T29	2		T30	7
auto[1]	values[8]	valids[0x0]	2472	1			T23	16		T32	13		T29	12
auto[1]	values[8]	valids[0x1]	1715	1			T23	14		T32	2		T29	4