Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17828

1

T4

13

T10

16

T6

135

auto[1]

20259

1

T6

419

T7

208

T8

8

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13458

1

T4

13

T10

16

T6

93

auto[1]

24629

1

T6

461

T7

247

T8

13

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	6333	1			T4	3		T10	2		T6	91
auto[524288:1048575]	3833	1			T4	3		T6	123		T7	68
auto[1048576:1572863]	5368	1			T6	158		T7	27		T23	28
auto[1572864:2097151]	4877	1			T10	4		T6	16		T7	11
auto[2097152:2621439]	4461	1			T10	7		T6	10		T7	44
auto[2621440:3145727]	4861	1			T6	38		T7	55		T8	11
auto[3145728:3670015]	4151	1			T4	7		T6	6		T7	68
auto[3670016:4194303]	4203	1			T10	3		T6	112		T7	39

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37538

1

T4

13

T10

16

T6

552

auto[1]

549

1

T6

2

T7

18

T23

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19632

1

T4

6

T10

4

T6

220

auto[1]

18455

1

T4

7

T10

12

T6

334

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1244	1			T4	2		T10	2		T6	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	678	1			T6	3		T7	2		T15	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	672	1			T4	1		T6	6		T7	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	377	1			T6	3		T7	2		T23	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	794	1			T6	4		T23	9		T16	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	425	1			T6	4		T7	1		T23	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	653	1			T10	2		T7	5		T24	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	367	1			T7	2		T14	1		T18	6
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	711	1			T6	1		T7	11		T14	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	350	1			T7	4		T14	1		T19	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	799	1			T6	7		T7	2		T8	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	444	1			T6	5		T8	2		T14	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	626	1			T4	3		T6	1		T7	13
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	334	1			T6	2		T7	6		T15	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	617	1			T6	3		T7	8		T23	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	355	1			T6	5		T7	4		T23	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	727	1			T4	1		T6	4		T7	10
auto[0]	auto[1]	auto[0:524287]	auto[1]	384	1			T6	4		T7	6		T8	3
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	562	1			T4	2		T6	7		T7	9
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	332	1			T6	4		T7	4		T23	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	687	1			T6	6		T7	10		T23	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	382	1			T6	6		T7	6		T23	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	734	1			T10	2		T6	7		T7	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	434	1			T6	9		T7	2		T8	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	630	1			T10	7		T6	5		T7	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	379	1			T6	4		T7	3		T14	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	671	1			T6	2		T7	9		T92	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	330	1			T6	2		T7	10		T23	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	687	1			T4	4		T6	2		T7	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	365	1			T6	1		T7	3		T14	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	677	1			T10	3		T6	13		T7	7
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	401	1			T6	10		T7	7		T23	3
auto[1]	auto[0]	auto[0:524287]	auto[0]	181	1			T6	2		T15	1		T19	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2241	1			T6	26		T15	6		T19	6
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	113	1			T6	2		T7	1		T19	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	819	1			T6	73		T7	27		T19	10
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	134	1			T6	2		T23	2		T18	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1363	1			T6	44		T23	5		T18	68
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	111	1			T18	2		T19	1		T22	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1101	1			T18	6		T19	12		T22	87
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	113	1			T93	1		T20	2		T30	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	932	1			T93	1		T20	99		T30	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	147	1			T6	2		T8	1		T14	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1204	1			T6	20		T8	7		T14	37
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	93	1			T7	5		T15	1		T16	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	739	1			T7	40		T15	10		T16	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	104	1			T23	1		T14	2		T18	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	791	1			T23	2		T14	18		T18	11
auto[1]	auto[1]	auto[0:524287]	auto[0]	109	1			T6	2		T7	3		T19	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	769	1			T6	45		T7	34		T19	14
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	102	1			T6	2		T7	3		T14	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	856	1			T6	26		T7	18		T14	8
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	137	1			T6	4		T7	2		T23	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1446	1			T6	88		T7	8		T23	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	140	1			T23	4		T14	2		T18	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1337	1			T23	13		T14	56		T18	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	137	1			T7	3		T14	1		T16	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1209	1			T7	17		T14	10		T16	34
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	114	1			T7	4		T14	6		T18	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1152	1			T7	30		T14	65		T18	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	111	1			T14	4		T19	2		T29	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1196	1			T14	94		T19	17		T29	22
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	121	1			T6	4		T7	2		T23	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1137	1			T6	77		T7	11		T23	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	9360	1			T4	6		T10	4		T6	49
auto[0]	auto[0]	auto[1]	86	1			T7	2		T19	4		T29	1
auto[0]	auto[1]	auto[0]	8302	1			T4	7		T10	12		T6	85
auto[0]	auto[1]	auto[1]	80	1			T6	1		T7	3		T14	1
auto[1]	auto[0]	auto[0]	9988	1			T6	171		T7	68		T8	8
auto[1]	auto[0]	auto[1]	198	1			T7	5		T19	9		T29	3
auto[1]	auto[1]	auto[0]	9888	1			T6	247		T7	127		T23	21
auto[1]	auto[1]	auto[1]	185	1			T6	1		T7	8		T23	1