Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_rx_size	8	1	7	87.50	100	1	1	0

Summary for Variable cp_rx_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for cp_rx_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
specific_sizes[4092]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
specific_sizes[4]	47908	1			T2	3		T11	2951		T26	2100
specific_sizes[2048]	175	1			T1	1		T46	103		T178	68
sizes[0]	69574	1			T2	3		T11	2951		T33	3
sizes[1]	5545	1			T179	8		T180	13		T150	39
sizes[2]	2220	1			T1	1		T106	100		T181	39
sizes[3]	411	1			T54	48		T42	74		T182	44
sizes[4]	98	1			T183	21		T184	41		T185	36