Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18734

1

T4

14

T10

18

T6

396

auto[1]

14214

1

T6

323

T7

246

T8

30

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3770	1			T6	160		T7	105		T14	107
values[1]	3726	1			T6	40		T7	54		T8	20
values[2]	4569	1			T6	20		T7	71		T14	136
values[3]	4716	1			T6	90		T7	20		T8	28
values[4]	4583	1			T6	20		T12	12		T24	8
values[5]	3351	1			T4	14		T7	55		T14	20
values[6]	4588	1			T10	18		T6	349		T7	217
values[7]	3645	1			T6	40		T7	86		T14	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4670	1			T6	67		T7	78		T14	98
values[1]	4592	1			T6	315		T8	28		T14	62
values[2]	3851	1			T6	122		T7	89		T12	12
values[3]	3759	1			T4	14		T6	40		T7	119
values[4]	3729	1			T10	18		T6	93		T7	20
values[5]	3816	1			T6	20		T8	20		T14	335
values[6]	4158	1			T7	60		T24	8		T14	173
values[7]	4373	1			T6	62		T7	242		T14	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	405	1			T6	4		T18	17		T100	13
auto[0]	values[0]	values[1]	301	1			T18	12		T250	22		T227	9
auto[0]	values[0]	values[2]	271	1			T7	35		T100	11		T259	2
auto[0]	values[0]	values[3]	190	1			T260	18		T247	20		T100	11
auto[0]	values[0]	values[4]	210	1			T6	10		T213	15		T261	8
auto[0]	values[0]	values[5]	261	1			T14	6		T18	7		T100	12
auto[0]	values[0]	values[6]	181	1			T7	13		T262	14		T226	14
auto[0]	values[0]	values[7]	256	1			T7	20		T101	8		T176	33
auto[0]	values[1]	values[0]	193	1			T14	10		T221	17		T212	17
auto[0]	values[1]	values[1]	423	1			T6	10		T18	13		T215	24
auto[0]	values[1]	values[2]	306	1			T207	14		T213	11		T226	42
auto[0]	values[1]	values[3]	257	1			T92	14		T18	29		T122	10
auto[0]	values[1]	values[4]	200	1			T7	11		T263	10		T248	9
auto[0]	values[1]	values[5]	155	1			T8	11		T14	14		T213	6
auto[0]	values[1]	values[6]	210	1			T264	16		T226	11		T221	49
auto[0]	values[1]	values[7]	297	1			T6	11		T7	14		T14	10
auto[0]	values[2]	values[0]	336	1			T7	29		T19	31		T20	13
auto[0]	values[2]	values[1]	417	1			T6	10		T15	11		T22	10
auto[0]	values[2]	values[2]	124	1			T111	20		T22	19		T100	9
auto[0]	values[2]	values[3]	343	1			T7	7		T18	10		T20	25
auto[0]	values[2]	values[4]	219	1			T265	85		T22	9		T207	14
auto[0]	values[2]	values[5]	444	1			T14	49		T18	10		T176	143
auto[0]	values[2]	values[6]	560	1			T14	11		T100	24		T266	193
auto[0]	values[2]	values[7]	258	1			T19	14		T175	78		T213	24
auto[0]	values[3]	values[0]	561	1			T14	12		T16	9		T19	12
auto[0]	values[3]	values[1]	177	1			T6	11		T8	7		T19	27
auto[0]	values[3]	values[2]	223	1			T6	8		T17	10		T176	9
auto[0]	values[3]	values[3]	304	1			T6	12		T14	11		T16	10
auto[0]	values[3]	values[4]	454	1			T18	13		T19	18		T208	9
auto[0]	values[3]	values[5]	202	1			T18	15		T19	12		T221	22
auto[0]	values[3]	values[6]	408	1			T7	13		T19	34		T101	7
auto[0]	values[3]	values[7]	290	1			T100	19		T208	10		T176	13
auto[0]	values[4]	values[0]	312	1			T19	11		T22	14		T175	13
auto[0]	values[4]	values[1]	366	1			T6	14		T14	51		T19	15
auto[0]	values[4]	values[2]	278	1			T12	12		T209	28		T207	42
auto[0]	values[4]	values[3]	240	1			T100	12		T227	7		T122	16
auto[0]	values[4]	values[4]	307	1			T14	10		T175	14		T267	22
auto[0]	values[4]	values[5]	334	1			T14	8		T15	25		T18	30
auto[0]	values[4]	values[6]	309	1			T24	8		T20	14		T268	73
auto[0]	values[4]	values[7]	415	1			T19	36		T269	32		T101	19
auto[0]	values[5]	values[0]	223	1			T207	103		T226	15		T270	11
auto[0]	values[5]	values[1]	291	1			T213	13		T176	17		T271	22
auto[0]	values[5]	values[2]	297	1			T7	15		T272	26		T213	10
auto[0]	values[5]	values[3]	328	1			T4	14		T20	62		T176	13
auto[0]	values[5]	values[4]	123	1			T19	10		T207	21		T215	10
auto[0]	values[5]	values[5]	143	1			T14	12		T19	15		T273	2
auto[0]	values[5]	values[6]	283	1			T100	8		T122	11		T221	10
auto[0]	values[5]	values[7]	318	1			T7	20		T18	11		T19	12
auto[0]	values[6]	values[0]	224	1			T7	11		T16	8		T100	16
auto[0]	values[6]	values[1]	479	1			T6	192		T16	14		T18	11
auto[0]	values[6]	values[2]	505	1			T6	87		T7	12		T274	24
auto[0]	values[6]	values[3]	332	1			T7	13		T208	13		T215	34
auto[0]	values[6]	values[4]	279	1			T10	18		T22	76		T275	14
auto[0]	values[6]	values[5]	239	1			T14	15		T213	29		T85	20
auto[0]	values[6]	values[6]	249	1			T7	15		T14	9		T175	12
auto[0]	values[6]	values[7]	326	1			T6	6		T7	69		T18	9
auto[0]	values[7]	values[0]	243	1			T7	11		T19	8		T175	8
auto[0]	values[7]	values[1]	210	1			T227	24		T226	68		T62	13
auto[0]	values[7]	values[2]	268	1			T276	20		T101	23		T277	8
auto[0]	values[7]	values[3]	125	1			T6	10		T7	54		T177	17
auto[0]	values[7]	values[4]	323	1			T18	22		T278	8		T175	68
auto[0]	values[7]	values[5]	242	1			T6	11		T19	34		T22	14
auto[0]	values[7]	values[6]	362	1			T14	5		T279	18		T215	9
auto[0]	values[7]	values[7]	325	1			T22	13		T280	22		T249	9
auto[1]	values[0]	values[0]	342	1			T6	63		T18	3		T100	7
auto[1]	values[0]	values[1]	163	1			T18	8		T227	11		T176	9
auto[1]	values[0]	values[2]	266	1			T7	7		T100	9		T215	8
auto[1]	values[0]	values[3]	112	1			T281	22		T100	9		T62	8
auto[1]	values[0]	values[4]	242	1			T6	83		T213	13		T248	22
auto[1]	values[0]	values[5]	238	1			T14	101		T18	13		T100	14
auto[1]	values[0]	values[6]	122	1			T7	7		T226	6		T282	9
auto[1]	values[0]	values[7]	210	1			T7	23		T101	12		T283	22
auto[1]	values[1]	values[0]	145	1			T14	10		T284	10		T221	9
auto[1]	values[1]	values[1]	227	1			T6	10		T18	21		T215	18
auto[1]	values[1]	values[2]	218	1			T285	30		T207	6		T213	9
auto[1]	values[1]	values[3]	328	1			T18	6		T122	74		T286	64
auto[1]	values[1]	values[4]	273	1			T7	9		T248	11		T286	33
auto[1]	values[1]	values[5]	147	1			T8	9		T14	28		T213	14
auto[1]	values[1]	values[6]	99	1			T226	9		T221	8		T62	6
auto[1]	values[1]	values[7]	248	1			T6	9		T7	20		T14	10
auto[1]	values[2]	values[0]	389	1			T7	9		T19	65		T20	152
auto[1]	values[2]	values[1]	303	1			T6	10		T15	9		T22	10
auto[1]	values[2]	values[2]	126	1			T22	10		T100	11		T208	6
auto[1]	values[2]	values[3]	231	1			T7	26		T18	14		T20	5
auto[1]	values[2]	values[4]	201	1			T22	11		T207	48		T211	24
auto[1]	values[2]	values[5]	249	1			T14	9		T18	10		T176	8
auto[1]	values[2]	values[6]	274	1			T14	67		T100	16		T213	12
auto[1]	values[2]	values[7]	95	1			T19	11		T175	11		T213	6
auto[1]	values[3]	values[0]	368	1			T14	66		T16	47		T19	8
auto[1]	values[3]	values[1]	188	1			T6	31		T8	21		T19	10
auto[1]	values[3]	values[2]	144	1			T6	20		T176	11		T221	15
auto[1]	values[3]	values[3]	395	1			T6	8		T14	9		T16	25
auto[1]	values[3]	values[4]	203	1			T18	60		T19	11		T208	19
auto[1]	values[3]	values[5]	207	1			T18	5		T19	8		T221	46
auto[1]	values[3]	values[6]	276	1			T7	7		T19	14		T101	23
auto[1]	values[3]	values[7]	316	1			T100	3		T208	10		T176	25
auto[1]	values[4]	values[0]	292	1			T19	26		T287	22		T22	6
auto[1]	values[4]	values[1]	180	1			T6	6		T14	11		T19	16
auto[1]	values[4]	values[2]	354	1			T207	9		T213	7		T215	10
auto[1]	values[4]	values[3]	208	1			T100	19		T227	16		T122	4
auto[1]	values[4]	values[4]	164	1			T14	10		T175	29		T207	10
auto[1]	values[4]	values[5]	407	1			T14	80		T15	13		T18	12
auto[1]	values[4]	values[6]	144	1			T20	6		T175	10		T207	27
auto[1]	values[4]	values[7]	273	1			T19	32		T101	21		T215	16
auto[1]	values[5]	values[0]	127	1			T207	10		T226	5		T270	17
auto[1]	values[5]	values[1]	305	1			T213	7		T176	3		T122	178
auto[1]	values[5]	values[2]	184	1			T7	12		T213	10		T176	11
auto[1]	values[5]	values[3]	183	1			T20	10		T176	7		T122	15
auto[1]	values[5]	values[4]	172	1			T19	49		T207	19		T243	22
auto[1]	values[5]	values[5]	68	1			T14	8		T19	14		T62	10
auto[1]	values[5]	values[6]	194	1			T100	12		T122	9		T221	10
auto[1]	values[5]	values[7]	112	1			T7	8		T18	9		T19	15
auto[1]	values[6]	values[0]	128	1			T7	9		T16	12		T100	6
auto[1]	values[6]	values[1]	434	1			T6	21		T16	28		T18	9
auto[1]	values[6]	values[2]	143	1			T6	7		T7	8		T122	29
auto[1]	values[6]	values[3]	145	1			T7	7		T208	7		T215	16
auto[1]	values[6]	values[4]	213	1			T22	8		T213	28		T215	8
auto[1]	values[6]	values[5]	175	1			T14	5		T213	16		T62	24
auto[1]	values[6]	values[6]	256	1			T7	5		T14	66		T175	36
auto[1]	values[6]	values[7]	461	1			T6	36		T7	68		T18	11
auto[1]	values[7]	values[0]	382	1			T7	9		T19	12		T175	105
auto[1]	values[7]	values[1]	128	1			T227	4		T226	7		T62	7
auto[1]	values[7]	values[2]	144	1			T101	13		T213	25		T270	8
auto[1]	values[7]	values[3]	38	1			T6	10		T7	12		T177	3
auto[1]	values[7]	values[4]	146	1			T18	10		T175	8		T177	4
auto[1]	values[7]	values[5]	305	1			T6	9		T19	51		T22	124
auto[1]	values[7]	values[6]	231	1			T14	15		T240	18		T215	11
auto[1]	values[7]	values[7]	173	1			T22	7		T249	11		T270	22