Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	12	0	12	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6566482	1			T4	1		T1	2		T2	2
all_pins[1]	6566482	1			T4	1		T1	2		T2	2
all_pins[2]	6566482	1			T4	1		T1	2		T2	2
all_pins[3]	6566482	1			T4	1		T1	2		T2	2
all_pins[4]	6566482	1			T4	1		T1	2		T2	2
all_pins[5]	6566482	1			T4	1		T1	2		T2	2
all_pins[6]	6566482	1			T4	1		T1	2		T2	2
all_pins[7]	6566482	1			T4	1		T1	2		T2	2
all_pins[8]	6566482	1			T4	1		T1	2		T2	2
all_pins[9]	6566482	1			T4	1		T1	2		T2	2
all_pins[10]	6566482	1			T4	1		T1	2		T2	2
all_pins[11]	6566482	1			T4	1		T1	2		T2	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	78650169	1			T4	12		T1	22		T2	21
values[0x1]	147615	1			T1	2		T2	3		T3	1
transitions[0x0=>0x1]	146458	1			T1	1		T2	2		T3	1
transitions[0x1=>0x0]	146473	1			T1	1		T2	2		T3	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6565941	1			T4	1		T1	2		T2	2
all_pins[0]	values[0x1]	541	1			T57	2		T58	1		T60	3
all_pins[0]	transitions[0x0=>0x1]	311	1			T57	1		T58	1		T60	3
all_pins[0]	transitions[0x1=>0x0]	137241	1			T1	1		T2	1		T59	1
all_pins[1]	values[0x0]	6429011	1			T4	1		T1	1		T2	1
all_pins[1]	values[0x1]	137471	1			T1	1		T2	1		T57	1
all_pins[1]	transitions[0x0=>0x1]	137346	1			T57	1		T59	1		T130	3
all_pins[1]	transitions[0x1=>0x0]	441	1			T3	1		T11	1		T57	2
all_pins[2]	values[0x0]	6565916	1			T4	1		T1	1		T2	1
all_pins[2]	values[0x1]	566	1			T1	1		T2	1		T3	1
all_pins[2]	transitions[0x0=>0x1]	537	1			T1	1		T2	1		T3	1
all_pins[2]	transitions[0x1=>0x0]	78	1			T57	1		T59	1		T60	1
all_pins[3]	values[0x0]	6566375	1			T4	1		T1	2		T2	2
all_pins[3]	values[0x1]	107	1			T57	1		T58	2		T59	1
all_pins[3]	transitions[0x0=>0x1]	88	1			T59	1		T60	1		T130	6
all_pins[3]	transitions[0x1=>0x0]	372	1			T2	1		T57	2		T59	1
all_pins[4]	values[0x0]	6566091	1			T4	1		T1	2		T2	1
all_pins[4]	values[0x1]	391	1			T2	1		T57	3		T58	2
all_pins[4]	transitions[0x0=>0x1]	223	1			T2	1		T57	3		T58	2
all_pins[4]	transitions[0x1=>0x0]	1804	1			T57	2		T58	1		T60	1
all_pins[5]	values[0x0]	6564510	1			T4	1		T1	2		T2	2
all_pins[5]	values[0x1]	1972	1			T57	2		T58	1		T60	1
all_pins[5]	transitions[0x0=>0x1]	1955	1			T57	2		T58	1		T130	1
all_pins[5]	transitions[0x1=>0x0]	1508	1			T57	1		T58	2		T59	1
all_pins[6]	values[0x0]	6564957	1			T4	1		T1	2		T2	2
all_pins[6]	values[0x1]	1525	1			T57	1		T58	2		T59	1
all_pins[6]	transitions[0x0=>0x1]	1100	1			T59	1		T60	3		T130	5
all_pins[6]	transitions[0x1=>0x0]	87	1			T57	1		T60	1		T186	2
all_pins[7]	values[0x0]	6565970	1			T4	1		T1	2		T2	2
all_pins[7]	values[0x1]	512	1			T57	2		T58	2		T60	1
all_pins[7]	transitions[0x0=>0x1]	471	1			T57	1		T60	1		T186	1
all_pins[7]	transitions[0x1=>0x0]	99	1			T59	1		T60	3		T130	3
all_pins[8]	values[0x0]	6566342	1			T4	1		T1	2		T2	2
all_pins[8]	values[0x1]	140	1			T57	1		T58	2		T59	1
all_pins[8]	transitions[0x0=>0x1]	114	1			T130	4		T186	3		T188	1
all_pins[8]	transitions[0x1=>0x0]	86	1			T57	2		T58	1		T60	2
all_pins[9]	values[0x0]	6566370	1			T4	1		T1	2		T2	2
all_pins[9]	values[0x1]	112	1			T57	3		T58	3		T59	1
all_pins[9]	transitions[0x0=>0x1]	80	1			T57	3		T58	3		T60	4
all_pins[9]	transitions[0x1=>0x0]	78	1			T59	3		T130	2		T188	2
all_pins[10]	values[0x0]	6566372	1			T4	1		T1	2		T2	2
all_pins[10]	values[0x1]	110	1			T59	4		T60	1		T130	3
all_pins[10]	transitions[0x0=>0x1]	91	1			T59	2		T60	1		T130	3
all_pins[10]	transitions[0x1=>0x0]	4149	1			T57	1		T60	1		T130	1
all_pins[11]	values[0x0]	6562314	1			T4	1		T1	2		T2	2
all_pins[11]	values[0x1]	4168	1			T57	1		T59	2		T60	1
all_pins[11]	transitions[0x0=>0x1]	4142	1			T57	1		T59	1		T130	1
all_pins[11]	transitions[0x1=>0x0]	530	1			T57	2		T58	1		T60	3