Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	439	1			T6	11		T7	9		T14	3
auto[ReadAddrCrossIntoMailbox]	296	1			T6	5		T7	5		T14	3
auto[ReadAddrCrossOutOfMailbox]	315	1			T6	3		T7	5		T14	4
auto[ReadAddrCrossAllMailbox]	218	1			T6	4		T7	4		T14	4
auto[ReadAddrOutsideMailbox]	3707	1			T6	24		T7	51		T12	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2458

1

T6

21

T7

38

T12

2

auto[1]

2517

1

T6

26

T7

36

T12

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	873	1			T6	8		T7	14		T12	4
read_ops[0x0b]	802	1			T6	12		T7	14		T8	1
read_ops[0x3b]	808	1			T6	4		T7	9		T8	1
read_ops[0x6b]	832	1			T6	7		T7	13		T8	1
read_ops[0xbb]	840	1			T6	7		T7	8		T8	1
read_ops[0xeb]	820	1			T6	9		T7	16		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T6	1		T14	1		T17	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T6	2		T17	1		T22	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T7	1		T16	1		T19	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T18	1		T215	1		T226	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T14	1		T16	1		T288	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T6	1		T288	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T14	2		T288	1		T215	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T6	1		T7	1		T19	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	318	1			T6	1		T7	4		T12	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T6	2		T7	8		T12	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T6	1		T16	1		T215	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T6	4		T100	1		T122	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T7	1		T227	1		T176	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T6	1		T15	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T7	2		T14	1		T19	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T6	1		T19	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T7	1		T19	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T6	1		T226	1		T286	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	320	1			T6	2		T7	4		T8	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T6	2		T7	6		T15	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T6	1		T207	1		T277	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T7	1		T277	1		T215	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T6	1		T7	1		T14	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T17	1		T19	1		T213	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T19	1		T208	1		T176	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T7	1		T100	1		T213	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T18	1		T208	1		T122	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T16	1		T207	1		T227	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T6	2		T7	2		T8	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T7	4		T14	3		T16	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T6	1		T7	1		T100	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T100	1		T213	2		T215	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T17	1		T18	1		T100	3
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T6	1		T7	1		T17	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T175	1		T100	2		T207	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T7	2		T19	1		T175	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T6	1		T7	1		T100	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T6	1		T7	1		T175	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	289	1			T6	1		T7	3		T14	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	320	1			T6	2		T7	4		T8	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T7	1		T16	1		T17	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T6	1		T7	1		T17	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T16	1		T18	1		T19	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T6	1		T7	1		T14	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T18	1		T22	1		T175	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T22	1		T207	1		T213	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T100	1		T176	1		T122	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T14	1		T19	1		T22	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T6	4		T7	4		T14	6
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	315	1			T6	1		T7	1		T8	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	53	1			T7	4		T175	3		T100	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T7	1		T14	2		T207	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T6	1		T14	1		T16	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T22	2		T100	1		T207	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T6	1		T16	1		T175	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T14	2		T19	1		T22	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T14	1		T22	1		T207	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T215	1		T122	1		T226	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T6	3		T7	8		T8	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T6	4		T7	3		T8	1