Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4721	1			T10	18		T6	62		T7	76
values[1]	4531	1			T6	113		T7	23		T92	14
values[2]	4345	1			T6	42		T7	38		T18	40
values[3]	3339	1			T6	142		T7	34		T8	48
values[4]	4483	1			T6	87		T7	88		T14	169
values[5]	4181	1			T6	114		T7	188		T14	156
values[6]	3780	1			T4	14		T6	20		T7	60
values[7]	3568	1			T6	139		T7	101		T14	88

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4796	1			T6	362		T7	81		T15	38
values[1]	4107	1			T7	23		T92	14		T14	20
values[2]	4323	1			T6	67		T7	40		T14	78
values[3]	3789	1			T10	18		T6	210		T7	53
values[4]	4057	1			T6	20		T7	207		T8	20
values[5]	3788	1			T4	14		T6	20		T7	94
values[6]	3692	1			T6	20		T7	62		T8	28
values[7]	4396	1			T6	20		T7	48		T14	222

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32427

1

T4

14

T10

18

T6

715

auto[1]

521

1

T6

4

T7

6

T8

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	514	1			T6	20		T20	72		T215	20
auto[0]	values[0]	values[1]	427	1			T19	20		T51	30		T209	28
auto[0]	values[0]	values[2]	845	1			T19	70		T22	136		T175	18
auto[0]	values[0]	values[3]	430	1			T10	18		T6	42		T18	34
auto[0]	values[0]	values[4]	584	1			T7	55		T18	42		T175	42
auto[0]	values[0]	values[5]	517	1			T7	20		T18	20		T19	20
auto[0]	values[0]	values[6]	845	1			T24	8		T18	20		T175	19
auto[0]	values[0]	values[7]	490	1			T14	20		T20	20		T208	20
auto[0]	values[1]	values[0]	509	1			T6	93		T15	37		T17	10
auto[0]	values[1]	values[1]	659	1			T7	22		T92	14		T18	20
auto[0]	values[1]	values[2]	525	1			T19	64		T22	40		T207	25
auto[0]	values[1]	values[3]	398	1			T18	35		T289	2		T100	20
auto[0]	values[1]	values[4]	502	1			T19	30		T22	84		T207	20
auto[0]	values[1]	values[5]	317	1			T14	60		T263	10		T122	23
auto[0]	values[1]	values[6]	715	1			T14	19		T20	163		T265	85
auto[0]	values[1]	values[7]	836	1			T6	20		T14	74		T290	10
auto[0]	values[2]	values[0]	890	1			T6	42		T19	56		T111	20
auto[0]	values[2]	values[1]	454	1			T213	19		T176	122		T122	20
auto[0]	values[2]	values[2]	420	1			T260	18		T226	47		T221	19
auto[0]	values[2]	values[3]	485	1			T18	20		T213	27		T215	27
auto[0]	values[2]	values[4]	505	1			T7	38		T175	87		T243	22
auto[0]	values[2]	values[5]	576	1			T22	39		T217	4		T176	68
auto[0]	values[2]	values[6]	372	1			T18	20		T100	18		T213	20
auto[0]	values[2]	values[7]	587	1			T207	20		T215	38		T176	57
auto[0]	values[3]	values[0]	412	1			T6	28		T250	22		T100	42
auto[0]	values[3]	values[1]	343	1			T14	20		T122	20		T284	10
auto[0]	values[3]	values[2]	387	1			T14	20		T16	56		T226	28
auto[0]	values[3]	values[3]	549	1			T6	94		T14	78		T16	20
auto[0]	values[3]	values[4]	360	1			T6	19		T8	18		T19	29
auto[0]	values[3]	values[5]	449	1			T7	33		T52	84		T278	8
auto[0]	values[3]	values[6]	263	1			T8	27		T100	19		T259	2
auto[0]	values[3]	values[7]	515	1			T101	20		T291	12		T262	14
auto[0]	values[4]	values[0]	656	1			T6	20		T274	24		T207	19
auto[0]	values[4]	values[1]	825	1			T18	31		T19	29		T175	20
auto[0]	values[4]	values[2]	471	1			T6	67		T213	20		T122	20
auto[0]	values[4]	values[3]	457	1			T7	20		T18	96		T175	76
auto[0]	values[4]	values[4]	547	1			T7	20		T14	42		T19	35
auto[0]	values[4]	values[5]	435	1			T7	20		T14	20		T226	40
auto[0]	values[4]	values[6]	482	1			T16	35		T264	16		T100	31
auto[0]	values[4]	values[7]	535	1			T7	28		T14	107		T261	8
auto[0]	values[5]	values[0]	605	1			T19	46		T20	82		T213	25
auto[0]	values[5]	values[1]	434	1			T19	28		T287	22		T292	30
auto[0]	values[5]	values[2]	416	1			T7	20		T14	58		T281	22
auto[0]	values[5]	values[3]	518	1			T6	74		T7	33		T19	59
auto[0]	values[5]	values[4]	723	1			T7	90		T100	15		T228	14
auto[0]	values[5]	values[5]	701	1			T6	20		T14	74		T100	40
auto[0]	values[5]	values[6]	252	1			T6	20		T7	42		T285	30
auto[0]	values[5]	values[7]	467	1			T14	20		T15	20		T293	8
auto[0]	values[6]	values[0]	532	1			T6	20		T7	20		T16	40
auto[0]	values[6]	values[1]	492	1			T19	20		T100	27		T277	8
auto[0]	values[6]	values[2]	753	1			T7	20		T18	20		T288	6
auto[0]	values[6]	values[3]	500	1			T100	23		T272	26		T84	22
auto[0]	values[6]	values[4]	431	1			T268	73		T22	48		T267	22
auto[0]	values[6]	values[5]	316	1			T4	14		T12	12		T14	20
auto[0]	values[6]	values[6]	344	1			T7	20		T21	14		T273	2
auto[0]	values[6]	values[7]	353	1			T19	46		T213	19		T226	20
auto[0]	values[7]	values[0]	595	1			T6	136		T7	61		T213	23
auto[0]	values[7]	values[1]	420	1			T18	20		T19	25		T215	20
auto[0]	values[7]	values[2]	435	1			T19	20		T22	40		T100	26
auto[0]	values[7]	values[3]	393	1			T175	113		T207	20		T101	20
auto[0]	values[7]	values[4]	344	1			T18	19		T100	20		T249	19
auto[0]	values[7]	values[5]	415	1			T7	20		T14	87		T207	20
auto[0]	values[7]	values[6]	358	1			T19	22		T100	19		T215	59
auto[0]	values[7]	values[7]	542	1			T7	20		T226	19		T62	20
auto[1]	values[0]	values[0]	7	1			T122	1		T221	1		T248	1
auto[1]	values[0]	values[1]	7	1			T177	1		T294	2		T295	1
auto[1]	values[0]	values[2]	15	1			T19	3		T22	2		T175	2
auto[1]	values[0]	values[3]	14	1			T227	6		T177	1		T148	1
auto[1]	values[0]	values[4]	11	1			T7	1		T175	1		T296	1
auto[1]	values[0]	values[5]	2	1			T235	2		-	-		-	-
auto[1]	values[0]	values[6]	5	1			T175	1		T101	1		T213	2
auto[1]	values[0]	values[7]	8	1			T62	3		T212	2		T297	1
auto[1]	values[1]	values[0]	4	1			T15	1		T235	2		T297	1
auto[1]	values[1]	values[1]	7	1			T7	1		T20	2		T100	1
auto[1]	values[1]	values[2]	8	1			T221	1		T62	1		T298	2
auto[1]	values[1]	values[3]	14	1			T226	1		T248	2		T299	6
auto[1]	values[1]	values[4]	6	1			T19	1		T176	1		T300	2
auto[1]	values[1]	values[5]	4	1			T14	2		T301	1		T302	1
auto[1]	values[1]	values[6]	12	1			T14	1		T20	2		T22	1
auto[1]	values[1]	values[7]	15	1			T14	1		T215	1		T214	3
auto[1]	values[2]	values[0]	4	1			T62	1		T296	2		T303	1
auto[1]	values[2]	values[1]	7	1			T213	1		T229	1		T304	3
auto[1]	values[2]	values[2]	10	1			T221	1		T242	1		T305	2
auto[1]	values[2]	values[3]	6	1			T213	1		T215	1		T305	1
auto[1]	values[2]	values[4]	5	1			T175	2		T306	3		-	-
auto[1]	values[2]	values[5]	9	1			T22	1		T122	2		T212	1
auto[1]	values[2]	values[6]	9	1			T100	2		T208	1		T221	1
auto[1]	values[2]	values[7]	6	1			T176	3		T235	1		T307	2
auto[1]	values[3]	values[0]	9	1			T100	2		T207	2		T205	3
auto[1]	values[3]	values[1]	7	1			T148	3		T248	1		T303	1
auto[1]	values[3]	values[2]	3	1			T308	1		T306	1		T309	1
auto[1]	values[3]	values[3]	3	1			T207	1		T310	2		-	-
auto[1]	values[3]	values[4]	9	1			T6	1		T8	2		T205	1
auto[1]	values[3]	values[5]	13	1			T7	1		T227	2		T213	2
auto[1]	values[3]	values[6]	8	1			T8	1		T100	1		T211	6
auto[1]	values[3]	values[7]	9	1			T249	3		T177	1		T301	2
auto[1]	values[4]	values[0]	23	1			T207	1		T176	2		T177	1
auto[1]	values[4]	values[1]	13	1			T18	1		T207	2		T226	1
auto[1]	values[4]	values[2]	7	1			T311	2		T212	2		T312	2
auto[1]	values[4]	values[3]	4	1			T18	1		T226	3		-	-
auto[1]	values[4]	values[4]	5	1			T19	2		T20	1		T122	2
auto[1]	values[4]	values[5]	7	1			T226	1		T205	3		T302	1
auto[1]	values[4]	values[6]	9	1			T215	3		T206	1		T313	1
auto[1]	values[4]	values[7]	7	1			T314	2		T315	1		T307	2
auto[1]	values[5]	values[0]	9	1			T19	1		T239	3		T206	2
auto[1]	values[5]	values[1]	5	1			T19	1		T177	1		T316	2
auto[1]	values[5]	values[2]	3	1			T122	1		T315	1		T317	1
auto[1]	values[5]	values[3]	4	1			T295	1		T318	3		-	-
auto[1]	values[5]	values[4]	10	1			T7	3		T100	5		T214	1
auto[1]	values[5]	values[5]	15	1			T14	4		T319	2		T320	4
auto[1]	values[5]	values[6]	2	1			T175	1		T225	1		-	-
auto[1]	values[5]	values[7]	17	1			T226	1		T229	4		T239	1
auto[1]	values[6]	values[0]	15	1			T16	2		T176	1		T235	2
auto[1]	values[6]	values[1]	5	1			T176	3		T62	1		T318	1
auto[1]	values[6]	values[2]	11	1			T101	1		T227	1		T176	2
auto[1]	values[6]	values[3]	6	1			T100	1		T314	2		T307	1
auto[1]	values[6]	values[4]	7	1			T173	1		T304	2		T282	1
auto[1]	values[6]	values[5]	5	1			T215	1		T62	2		T214	1
auto[1]	values[6]	values[6]	4	1			T21	2		T235	1		T297	1
auto[1]	values[6]	values[7]	6	1			T19	2		T213	1		T239	2
auto[1]	values[7]	values[0]	12	1			T6	3		T213	2		T208	1
auto[1]	values[7]	values[1]	2	1			T19	1		T212	1		-	-
auto[1]	values[7]	values[2]	14	1			T215	3		T238	2		T304	1
auto[1]	values[7]	values[3]	8	1			T214	2		T238	2		T314	4
auto[1]	values[7]	values[4]	8	1			T18	1		T249	1		T215	1
auto[1]	values[7]	values[5]	7	1			T14	1		T206	2		T321	4
auto[1]	values[7]	values[6]	12	1			T19	1		T100	1		T215	1
auto[1]	values[7]	values[7]	3	1			T226	1		T225	1		T322	1