Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2303

1

T7

1

T13

3

T8

2

auto[1]

2337

1

T7

2

T13

7

T23

18

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2248

1

T7

2

T13

6

T8

2

auto[1]

2392

1

T7

1

T13

4

T23

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3798

1

T7

2

T13

5

T23

18

auto[1]

842

1

T7

1

T13

5

T8

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	884	1			T13	3		T23	5		T15	4
valid[1]	948	1			T13	1		T23	3		T15	4
valid[2]	908	1			T7	2		T23	9		T15	4
valid[3]	977	1			T7	1		T13	1		T8	1
valid[4]	923	1			T13	5		T8	1		T23	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	125	1			T15	2		T93	3		T191	3
auto[0]	auto[0]	valid[0]	auto[1]	225	1			T90	2		T97	4		T98	1
auto[0]	auto[0]	valid[1]	auto[0]	153	1			T23	1		T15	1		T326	1
auto[0]	auto[0]	valid[1]	auto[1]	247	1			T13	1		T23	1		T89	2
auto[0]	auto[0]	valid[2]	auto[0]	130	1			T7	1		T23	1		T15	2
auto[0]	auto[0]	valid[2]	auto[1]	242	1			T23	2		T90	2		T93	1
auto[0]	auto[0]	valid[3]	auto[0]	135	1			T91	1		T93	1		T191	1
auto[0]	auto[0]	valid[3]	auto[1]	235	1			T90	1		T91	1		T97	3
auto[0]	auto[0]	valid[4]	auto[0]	153	1			T13	1		T23	2		T15	2
auto[0]	auto[0]	valid[4]	auto[1]	251	1			T89	1		T90	1		T97	1
auto[0]	auto[1]	valid[0]	auto[0]	138	1			T23	3		T18	1		T326	3
auto[0]	auto[1]	valid[0]	auto[1]	238	1			T13	1		T23	1		T89	1
auto[0]	auto[1]	valid[1]	auto[0]	156	1			T23	1		T15	3		T326	1
auto[0]	auto[1]	valid[1]	auto[1]	220	1			T89	1		T90	2		T91	1
auto[0]	auto[1]	valid[2]	auto[0]	126	1			T23	3		T15	2		T16	1
auto[0]	auto[1]	valid[2]	auto[1]	230	1			T7	1		T89	1		T93	1
auto[0]	auto[1]	valid[3]	auto[0]	152	1			T23	1		T15	2		T91	1
auto[0]	auto[1]	valid[3]	auto[1]	286	1			T89	2		T90	1		T97	7
auto[0]	auto[1]	valid[4]	auto[0]	138	1			T23	2		T15	3		T16	2
auto[0]	auto[1]	valid[4]	auto[1]	218	1			T13	2		T90	1		T91	1
auto[1]	auto[0]	valid[0]	auto[0]	82	1			T13	1		T23	1		T15	2
auto[1]	auto[0]	valid[1]	auto[0]	81	1			T18	1		T93	1		T191	1
auto[1]	auto[0]	valid[2]	auto[0]	88	1			T23	1		T93	4		T326	1
auto[1]	auto[0]	valid[3]	auto[0]	75	1			T8	1		T23	1		T15	1
auto[1]	auto[0]	valid[4]	auto[0]	81	1			T8	1		T23	1		T18	1
auto[1]	auto[1]	valid[0]	auto[0]	76	1			T13	1		T326	1		T192	1
auto[1]	auto[1]	valid[1]	auto[0]	91	1			T16	1		T18	1		T93	1
auto[1]	auto[1]	valid[2]	auto[0]	92	1			T23	2		T93	1		T326	1
auto[1]	auto[1]	valid[3]	auto[0]	94	1			T7	1		T13	1		T23	4
auto[1]	auto[1]	valid[4]	auto[0]	82	1			T13	2		T23	1		T15	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal