Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	72	2	70	97.22

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	72	2	70	97.22	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	430	1			T57	7		T58	4		T59	4
all_values[1]	430	1			T57	7		T58	4		T59	4
all_values[2]	430	1			T57	7		T58	4		T59	4
all_values[3]	430	1			T57	7		T58	4		T59	4
all_values[4]	430	1			T57	7		T58	4		T59	4
all_values[5]	430	1			T57	7		T58	4		T59	4
all_values[6]	430	1			T57	7		T58	4		T59	4
all_values[7]	430	1			T57	7		T58	4		T59	4
all_values[8]	430	1			T57	7		T58	4		T59	4
all_values[9]	430	1			T57	7		T58	4		T59	4
all_values[10]	430	1			T57	7		T58	4		T59	4
all_values[11]	430	1			T57	7		T58	4		T59	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2793

1

T57

54

T58

20

T59

33

auto[1]

2367

1

T57

30

T58

28

T59

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1985

1

T57

35

T58

19

T59

21

auto[1]

3175

1

T57

49

T58

29

T59

27

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2911

1

T57

47

T58

28

T59

30

auto[1]

2249

1

T57

37

T58

20

T59

18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	2	70	97.22	2
Automatically Generated Cross Bins	72	2	70	97.22	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[11]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	85	1			T57	1		T59	2		T60	2
all_values[0]	auto[0]	auto[0]	auto[1]	43	1			T57	2		T59	1		T60	1
all_values[0]	auto[0]	auto[1]	auto[0]	70	1			T57	1		T58	2		T60	2
all_values[0]	auto[0]	auto[1]	auto[1]	44	1			T57	1		T58	1		T60	1
all_values[0]	auto[1]	auto[0]	auto[1]	95	1			T57	1		T59	1		T60	1
all_values[0]	auto[1]	auto[1]	auto[1]	93	1			T57	1		T58	1		T60	3
all_values[1]	auto[0]	auto[0]	auto[0]	80	1			T57	1		T60	1		T130	1
all_values[1]	auto[0]	auto[0]	auto[1]	42	1			T58	1		T60	3		T186	1
all_values[1]	auto[0]	auto[1]	auto[0]	73	1			T57	2		T58	2		T59	2
all_values[1]	auto[0]	auto[1]	auto[1]	43	1			T57	1		T130	1		T186	2
all_values[1]	auto[1]	auto[0]	auto[1]	93	1			T57	1		T58	1		T59	1
all_values[1]	auto[1]	auto[1]	auto[1]	99	1			T57	2		T59	1		T60	3
all_values[2]	auto[0]	auto[0]	auto[0]	97	1			T57	2		T58	1		T59	3
all_values[2]	auto[0]	auto[0]	auto[1]	31	1			T130	2		T187	1		T171	1
all_values[2]	auto[0]	auto[1]	auto[0]	77	1			T60	2		T130	1		T186	5
all_values[2]	auto[0]	auto[1]	auto[1]	37	1			T57	1		T58	1		T60	1
all_values[2]	auto[1]	auto[0]	auto[1]	110	1			T57	3		T58	1		T59	1
all_values[2]	auto[1]	auto[1]	auto[1]	78	1			T57	1		T58	1		T60	2
all_values[3]	auto[0]	auto[0]	auto[0]	87	1			T57	2		T59	1		T60	2
all_values[3]	auto[0]	auto[0]	auto[1]	37	1			T60	1		T186	1		T188	1
all_values[3]	auto[0]	auto[1]	auto[0]	76	1			T57	2		T59	1		T60	3
all_values[3]	auto[0]	auto[1]	auto[1]	41	1			T58	1		T59	1		T130	2
all_values[3]	auto[1]	auto[0]	auto[1]	109	1			T57	1		T58	2		T59	1
all_values[3]	auto[1]	auto[1]	auto[1]	80	1			T57	2		T58	1		T60	2
all_values[4]	auto[0]	auto[0]	auto[0]	87	1			T57	2		T60	2		T130	4
all_values[4]	auto[0]	auto[0]	auto[1]	51	1			T59	1		T60	1		T130	4
all_values[4]	auto[0]	auto[1]	auto[0]	61	1			T57	1		T59	1		T60	1
all_values[4]	auto[0]	auto[1]	auto[1]	48	1			T57	1		T58	1		T60	1
all_values[4]	auto[1]	auto[0]	auto[1]	108	1			T57	1		T58	2		T59	1
all_values[4]	auto[1]	auto[1]	auto[1]	75	1			T57	2		T58	1		T59	1
all_values[5]	auto[0]	auto[0]	auto[0]	88	1			T58	2		T59	4		T60	3
all_values[5]	auto[0]	auto[0]	auto[1]	54	1			T57	2		T130	2		T186	2
all_values[5]	auto[0]	auto[1]	auto[0]	63	1			T60	2		T186	1		T188	1
all_values[5]	auto[0]	auto[1]	auto[1]	38	1			T60	1		T186	3		T171	4
all_values[5]	auto[1]	auto[0]	auto[1]	114	1			T57	4		T58	2		T60	3
all_values[5]	auto[1]	auto[1]	auto[1]	73	1			T57	1		T60	1		T130	2
all_values[6]	auto[0]	auto[0]	auto[0]	84	1			T57	3		T60	1		T130	1
all_values[6]	auto[0]	auto[0]	auto[1]	44	1			T57	1		T59	1		T60	1
all_values[6]	auto[0]	auto[1]	auto[0]	79	1			T58	2		T60	2		T130	1
all_values[6]	auto[0]	auto[1]	auto[1]	39	1			T58	1		T130	5		T186	1
all_values[6]	auto[1]	auto[0]	auto[1]	106	1			T57	2		T59	3		T60	2
all_values[6]	auto[1]	auto[1]	auto[1]	78	1			T57	1		T58	1		T60	4
all_values[7]	auto[0]	auto[0]	auto[0]	98	1			T57	3		T58	2		T59	2
all_values[7]	auto[0]	auto[0]	auto[1]	35	1			T60	2		T188	1		T166	2
all_values[7]	auto[0]	auto[1]	auto[0]	73	1			T59	1		T60	1		T130	3
all_values[7]	auto[0]	auto[1]	auto[1]	41	1			T58	1		T130	1		T166	1
all_values[7]	auto[1]	auto[0]	auto[1]	94	1			T57	2		T59	1		T60	3
all_values[7]	auto[1]	auto[1]	auto[1]	89	1			T57	2		T58	1		T60	2
all_values[8]	auto[0]	auto[0]	auto[0]	108	1			T57	1		T58	2		T60	2
all_values[8]	auto[0]	auto[0]	auto[1]	44	1			T57	1		T59	3		T130	2
all_values[8]	auto[0]	auto[1]	auto[0]	70	1			T57	2		T60	4		T186	2
all_values[8]	auto[0]	auto[1]	auto[1]	41	1			T58	1		T60	1		T130	3
all_values[8]	auto[1]	auto[0]	auto[1]	81	1			T57	2		T59	1		T130	4
all_values[8]	auto[1]	auto[1]	auto[1]	86	1			T57	1		T58	1		T60	3
all_values[9]	auto[0]	auto[0]	auto[0]	80	1			T59	1		T60	3		T130	1
all_values[9]	auto[0]	auto[0]	auto[1]	43	1			T57	2		T60	1		T130	1
all_values[9]	auto[0]	auto[1]	auto[0]	63	1			T59	2		T130	3		T186	2
all_values[9]	auto[0]	auto[1]	auto[1]	44	1			T58	1		T60	3		T130	1
all_values[9]	auto[1]	auto[0]	auto[1]	102	1			T57	3		T59	1		T60	1
all_values[9]	auto[1]	auto[1]	auto[1]	98	1			T57	2		T58	3		T60	2
all_values[10]	auto[0]	auto[0]	auto[0]	72	1			T57	4		T187	1		T188	2
all_values[10]	auto[0]	auto[0]	auto[1]	37	1			T60	2		T166	3		T172	1
all_values[10]	auto[0]	auto[1]	auto[0]	72	1			T57	2		T58	2		T130	3
all_values[10]	auto[0]	auto[1]	auto[1]	49	1			T59	2		T60	1		T130	2
all_values[10]	auto[1]	auto[0]	auto[1]	114	1			T57	1		T58	2		T59	1
all_values[10]	auto[1]	auto[1]	auto[1]	86	1			T59	1		T60	1		T130	3
all_values[11]	auto[0]	auto[0]	auto[0]	132	1			T57	5		T58	2		T59	1
all_values[11]	auto[0]	auto[1]	auto[0]	110	1			T57	1		T58	2		T60	4
all_values[11]	auto[1]	auto[0]	auto[1]	108	1			T57	1		T59	1		T60	1
all_values[11]	auto[1]	auto[1]	auto[1]	80	1			T59	2		T60	2		T186	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal