Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57153

1

T7

74

T13

153

T8

123

auto[1]

24638

1

T7

12

T13

57

T23

77

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61037

1

T7

63

T13

139

T8

81

auto[1]

20754

1

T7

23

T13

71

T8

42

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	42009	1			T7	42		T13	119		T8	62
others[1]	6809	1			T7	10		T13	12		T8	12
others[2]	6913	1			T7	3		T13	22		T8	12
others[3]	7850	1			T7	10		T13	17		T8	15
interest[1]	4662	1			T7	4		T13	13		T8	3
interest[4]	27313	1			T7	34		T13	77		T8	38
interest[64]	13548	1			T7	17		T13	27		T8	19

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	18657	1			T7	23		T13	47		T8	35
auto[0]	auto[0]	others[1]	2930	1			T7	7		T13	3		T8	9
auto[0]	auto[0]	others[2]	3068	1			T7	1		T13	10		T8	7
auto[0]	auto[0]	others[3]	3516	1			T7	5		T13	6		T8	10
auto[0]	auto[0]	interest[1]	2039	1			T7	3		T13	4		T8	3
auto[0]	auto[0]	interest[4]	11978	1			T7	20		T13	31		T8	21
auto[0]	auto[0]	interest[64]	6189	1			T7	12		T13	12		T8	17
auto[0]	auto[1]	others[0]	12696	1			T7	8		T13	31		T23	32
auto[0]	auto[1]	others[1]	2122	1			T7	1		T13	3		T23	7
auto[0]	auto[1]	others[2]	2063	1			T13	4		T23	9		T93	12
auto[0]	auto[1]	others[3]	2383	1			T7	1		T13	6		T23	12
auto[0]	auto[1]	interest[1]	1426	1			T7	1		T13	4		T23	2
auto[0]	auto[1]	interest[4]	8431	1			T7	6		T13	21		T23	21
auto[0]	auto[1]	interest[64]	3948	1			T7	1		T13	9		T23	15
auto[1]	auto[0]	others[0]	10656	1			T7	11		T13	41		T8	27
auto[1]	auto[0]	others[1]	1757	1			T7	2		T13	6		T8	3
auto[1]	auto[0]	others[2]	1782	1			T7	2		T13	8		T8	5
auto[1]	auto[0]	others[3]	1951	1			T7	4		T13	5		T8	5
auto[1]	auto[0]	interest[1]	1197	1			T13	5		T23	16		T15	5
auto[1]	auto[0]	interest[4]	6904	1			T7	8		T13	25		T8	17
auto[1]	auto[0]	interest[64]	3411	1			T7	4		T13	6		T8	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal