Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::all_modes_cg

Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	5	0	5	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_tpm_enabled	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	5	0	5	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[GenericMode]	7130256	1			T1	1534		T2	12		T3	81
auto[FlashMode]	87489	1			T13	210		T23	871		T32	22
auto[PassthroughMode]	57235	1			T4	22		T10	24		T6	719

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Summary for Variable cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tpm_enabled

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6798842

1

T4

22

T1

1534

T2

12

auto[1]

476138

1

T7

694

T13

210

T8

171

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Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	5	0	5	100.00
Automatically Generated Cross Bins	5	0	5	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_mode	cp_tpm_enabled	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[GenericMode]	auto[0]	6772578	1			T1	1534		T2	12		T3	81
auto[FlashMode]	auto[0]	10061	1			T32	22		T29	208		T151	20
auto[FlashMode]	auto[1]	77428	1			T13	210		T23	871		T89	8
auto[PassthroughMode]	auto[0]	16203	1			T4	22		T10	24		T6	719
auto[PassthroughMode]	auto[1]	41032	1			T7	694		T8	171		T15	616

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded