Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6078887	1			T1	2		T4	1		T2	2
all_values[1]	6078887	1			T1	2		T4	1		T2	2
all_values[2]	6078887	1			T1	2		T4	1		T2	2
all_values[3]	6078887	1			T1	2		T4	1		T2	2
all_values[4]	6078887	1			T1	2		T4	1		T2	2
all_values[5]	6078887	1			T1	2		T4	1		T2	2
all_values[6]	6078887	1			T1	2		T4	1		T2	2
all_values[7]	6078887	1			T1	2		T4	1		T2	2
all_values[8]	6078887	1			T1	2		T4	1		T2	2
all_values[9]	6078887	1			T1	2		T4	1		T2	2
all_values[10]	6078887	1			T1	2		T4	1		T2	2
all_values[11]	6078887	1			T1	2		T4	1		T2	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71525934

1

T1

14

T4

12

T2

10

auto[1]

1420710

1

T1

10

T2

14

T3

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72885571

1

T1

24

T4

12

T2

24

auto[1]

61073

1

T3

547

T76

8

T77

20

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6041280	1			T4	1		T3	55709		T13	2078
all_values[0]	auto[0]	auto[1]	123	1			T76	4		T97	1		T99	1
all_values[0]	auto[1]	auto[0]	37380	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	104	1			T77	2		T79	1		T97	5
all_values[1]	auto[0]	auto[0]	6023576	1			T1	2		T4	1		T3	55711
all_values[1]	auto[0]	auto[1]	119	1			T76	3		T77	2		T79	1
all_values[1]	auto[1]	auto[0]	55121	1			T2	2		T78	5		T79	1
all_values[1]	auto[1]	auto[1]	71	1			T98	5		T173	3		T207	1
all_values[2]	auto[0]	auto[0]	5939805	1			T1	2		T4	1		T2	2
all_values[2]	auto[0]	auto[1]	113	1			T77	1		T79	1		T97	2
all_values[2]	auto[1]	auto[0]	138871	1			T3	2		T76	1		T77	1
all_values[2]	auto[1]	auto[1]	98	1			T77	2		T78	4		T79	3
all_values[3]	auto[0]	auto[0]	5991780	1			T1	2		T4	1		T2	2
all_values[3]	auto[0]	auto[1]	101	1			T77	4		T98	3		T99	1
all_values[3]	auto[1]	auto[0]	86874	1			T76	5		T78	3		T98	2
all_values[3]	auto[1]	auto[1]	132	1			T78	2		T79	1		T97	3
all_values[4]	auto[0]	auto[0]	5922742	1			T1	2		T4	1		T2	2
all_values[4]	auto[0]	auto[1]	125	1			T77	1		T78	1		T98	1
all_values[4]	auto[1]	auto[0]	155928	1			T76	1		T77	1		T78	1
all_values[4]	auto[1]	auto[1]	92	1			T78	2		T79	3		T98	1
all_values[5]	auto[0]	auto[0]	5914016	1			T1	2		T4	1		T2	2
all_values[5]	auto[0]	auto[1]	108	1			T77	1		T78	1		T79	1
all_values[5]	auto[1]	auto[0]	164658	1			T3	2		T7	2		T76	1
all_values[5]	auto[1]	auto[1]	105	1			T78	2		T79	3		T97	1
all_values[6]	auto[0]	auto[0]	5914851	1			T4	1		T3	55350		T13	2078
all_values[6]	auto[0]	auto[1]	34111	1			T3	359		T79	2		T97	1
all_values[6]	auto[1]	auto[0]	129308	1			T1	2		T2	2		T3	2
all_values[6]	auto[1]	auto[1]	617	1			T97	1		T99	2		T172	3
all_values[7]	auto[0]	auto[0]	5966037	1			T4	1		T3	55554		T13	2078
all_values[7]	auto[0]	auto[1]	17141	1			T3	155		T78	1		T98	2
all_values[7]	auto[1]	auto[0]	95360	1			T1	2		T2	2		T3	2
all_values[7]	auto[1]	auto[1]	349	1			T79	1		T98	1		T99	1
all_values[8]	auto[0]	auto[0]	5967882	1			T4	1		T3	55678		T13	2078
all_values[8]	auto[0]	auto[1]	6519	1			T3	33		T79	1		T97	3
all_values[8]	auto[1]	auto[0]	104200	1			T1	2		T2	2		T76	1
all_values[8]	auto[1]	auto[1]	286	1			T77	3		T78	2		T99	1
all_values[9]	auto[0]	auto[0]	5914113	1			T1	2		T4	1		T2	2
all_values[9]	auto[0]	auto[1]	106	1			T78	1		T97	2		T98	2
all_values[9]	auto[1]	auto[0]	164568	1			T77	3		T78	3		T79	1
all_values[9]	auto[1]	auto[1]	100	1			T77	1		T79	4		T97	1
all_values[10]	auto[0]	auto[0]	5957216	1			T4	1		T3	55711		T13	2078
all_values[10]	auto[0]	auto[1]	110	1			T77	1		T79	2		T98	3
all_values[10]	auto[1]	auto[0]	121480	1			T1	2		T2	2		T7	2
all_values[10]	auto[1]	auto[1]	81	1			T97	2		T98	2		T207	5
all_values[11]	auto[0]	auto[0]	5913689	1			T1	2		T4	1		T3	55709
all_values[11]	auto[0]	auto[1]	271	1			T77	1		T78	1		T79	1
all_values[11]	auto[1]	auto[0]	164836	1			T2	2		T3	2		T7	2
all_values[11]	auto[1]	auto[1]	91	1			T76	1		T77	1		T78	1