Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.11 99.02 96.33 98.63 92.06 98.07 95.86 99.76


Total tests in report: 1782
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
79.10 79.10 97.45 97.45 89.85 89.85 68.88 68.88 75.41 75.41 96.44 96.44 83.90 83.90 41.73 41.73 /workspace/coverage/default/34.spi_device_stress_all.150578607
84.51 5.41 98.36 0.91 90.84 0.99 69.67 0.78 93.44 18.03 97.41 0.97 84.34 0.44 57.50 15.77 /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1372958921
89.10 4.59 98.41 0.05 92.72 1.88 88.85 19.18 93.44 0.00 97.44 0.03 93.65 9.31 59.17 1.67 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1711600861
90.32 1.22 98.43 0.02 93.38 0.66 89.04 0.20 93.44 0.00 97.48 0.03 93.65 0.00 66.79 7.62 /workspace/coverage/default/39.spi_device_stress_all.40842210
91.43 1.12 98.83 0.40 93.69 0.32 90.80 1.76 93.44 0.00 97.48 0.00 93.65 0.00 72.13 5.34 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3987493322
92.18 0.75 98.83 0.00 93.69 0.00 90.80 0.00 93.44 0.00 97.48 0.00 93.65 0.00 77.37 5.24 /workspace/coverage/default/40.spi_device_flash_and_tpm.2622302250
92.79 0.61 98.83 0.00 93.69 0.00 90.80 0.00 93.44 0.00 97.48 0.00 93.65 0.00 81.66 4.29 /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1754425673
93.35 0.56 98.84 0.01 93.69 0.00 94.72 3.91 93.44 0.00 97.48 0.00 93.65 0.00 81.66 0.00 /workspace/coverage/default/10.spi_device_ram_cfg.1264761463
93.91 0.56 98.84 0.00 93.76 0.06 97.65 2.94 93.44 0.00 97.48 0.00 94.53 0.89 81.66 0.00 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3017297675
94.28 0.37 98.84 0.00 94.63 0.88 98.04 0.39 93.44 0.00 97.49 0.02 94.83 0.30 82.66 1.00 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2062204787
94.62 0.34 98.85 0.01 94.63 0.00 98.04 0.00 93.44 0.00 97.51 0.02 94.83 0.00 85.04 2.38 /workspace/coverage/default/26.spi_device_flash_and_tpm.3160030739
94.93 0.31 98.85 0.00 94.63 0.00 98.04 0.00 93.44 0.00 97.51 0.00 94.83 0.00 87.18 2.14 /workspace/coverage/default/9.spi_device_flash_and_tpm.3915024729
95.18 0.25 98.88 0.04 94.68 0.05 98.04 0.00 95.08 1.64 97.56 0.05 94.83 0.00 87.18 0.00 /workspace/coverage/default/14.spi_device_rx_timeout.3021848047
95.43 0.25 98.88 0.00 94.68 0.00 98.04 0.00 95.08 0.00 97.56 0.00 94.83 0.00 88.90 1.72 /workspace/coverage/default/48.spi_device_flash_all.2594499701
95.67 0.24 99.00 0.11 95.13 0.44 98.04 0.00 95.08 0.00 97.71 0.15 95.42 0.59 89.28 0.38 /workspace/coverage/default/26.spi_device_flash_mode.4236370257
95.90 0.23 99.00 0.00 95.13 0.00 98.24 0.20 95.08 0.00 97.71 0.00 95.42 0.00 90.71 1.43 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2550378332
96.06 0.16 99.00 0.00 95.13 0.00 98.24 0.00 95.08 0.00 97.71 0.00 95.42 0.00 91.85 1.14 /workspace/coverage/default/0.spi_device_flash_all.85655132
96.21 0.15 99.03 0.03 95.53 0.41 98.24 0.00 95.08 0.00 97.76 0.05 95.57 0.15 92.28 0.43 /workspace/coverage/default/16.spi_device_stress_all.2188882303
96.34 0.13 99.05 0.03 95.57 0.04 98.24 0.00 95.08 0.00 97.82 0.05 95.57 0.00 93.04 0.76 /workspace/coverage/default/3.spi_device_stress_all.2557752468
96.45 0.11 99.05 0.00 95.57 0.00 98.24 0.00 95.08 0.00 97.82 0.00 95.57 0.00 93.81 0.76 /workspace/coverage/default/8.spi_device_flash_all.4104133552
96.55 0.10 99.08 0.03 95.78 0.20 98.24 0.00 95.08 0.00 97.88 0.07 95.57 0.00 94.24 0.43 /workspace/coverage/default/48.spi_device_extreme_fifo_size.365311632
96.65 0.09 99.08 0.00 95.80 0.03 98.63 0.39 95.08 0.00 97.88 0.00 95.72 0.15 94.33 0.10 /workspace/coverage/default/0.spi_device_sec_cm.1307706521
96.73 0.08 99.08 0.00 95.80 0.00 98.63 0.00 95.08 0.00 97.88 0.00 95.72 0.00 94.90 0.57 /workspace/coverage/default/31.spi_device_flash_and_tpm.3141207618
96.80 0.07 99.08 0.00 95.80 0.00 98.63 0.00 95.08 0.00 97.88 0.00 95.72 0.00 95.43 0.52 /workspace/coverage/default/14.spi_device_stress_all.1972280604
96.88 0.07 99.08 0.00 95.80 0.00 98.63 0.00 95.08 0.00 97.88 0.00 95.72 0.00 95.95 0.52 /workspace/coverage/default/41.spi_device_flash_all.1211279756
96.95 0.07 99.08 0.00 95.80 0.00 98.63 0.00 95.08 0.00 97.88 0.00 95.72 0.00 96.43 0.48 /workspace/coverage/default/6.spi_device_stress_all.3424995837
97.00 0.05 99.08 0.00 95.80 0.00 98.63 0.00 95.08 0.00 97.88 0.00 95.72 0.00 96.81 0.38 /workspace/coverage/default/11.spi_device_bit_transfer.723651678
97.04 0.04 99.08 0.00 95.86 0.06 98.63 0.00 95.08 0.00 97.88 0.00 95.72 0.00 97.05 0.24 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3514657789
97.08 0.04 99.08 0.00 95.86 0.00 98.63 0.00 95.08 0.00 97.88 0.00 95.72 0.00 97.33 0.29 /workspace/coverage/default/19.spi_device_flash_and_tpm.111753461
97.12 0.04 99.08 0.00 95.86 0.00 98.63 0.00 95.08 0.00 97.90 0.02 95.72 0.00 97.57 0.24 /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.305007949
97.15 0.03 99.08 0.00 95.86 0.00 98.63 0.00 95.08 0.00 97.90 0.00 95.72 0.00 97.81 0.24 /workspace/coverage/default/10.spi_device_stress_all.115356106
97.19 0.03 99.08 0.00 95.86 0.00 98.63 0.00 95.08 0.00 97.90 0.00 95.72 0.00 98.05 0.24 /workspace/coverage/default/43.spi_device_flash_and_tpm.3060852902
97.22 0.03 99.14 0.06 95.95 0.09 98.63 0.00 95.08 0.00 97.98 0.08 95.72 0.00 98.05 0.00 /workspace/coverage/default/14.spi_device_mem_parity.2434623504
97.25 0.03 99.14 0.00 96.05 0.10 98.63 0.00 95.08 0.00 98.00 0.02 95.72 0.00 98.14 0.10 /workspace/coverage/default/21.spi_device_flash_all.81078064
97.28 0.03 99.14 0.00 96.05 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.72 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2759548167
97.31 0.03 99.14 0.00 96.05 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.72 0.00 98.52 0.19 /workspace/coverage/default/28.spi_device_flash_all.2147918089
97.33 0.03 99.14 0.00 96.05 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.72 0.00 98.71 0.19 /workspace/coverage/default/47.spi_device_flash_and_tpm.3999870688
97.35 0.02 99.14 0.00 96.05 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.15 98.71 0.00 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3651852925
97.37 0.02 99.14 0.00 96.18 0.13 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 98.71 0.00 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2654244582
97.39 0.02 99.14 0.00 96.24 0.06 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 98.76 0.05 /workspace/coverage/default/42.spi_device_bit_transfer.902096832
97.40 0.01 99.14 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 98.86 0.10 /workspace/coverage/default/0.spi_device_flash_mode.3266308850
97.42 0.01 99.14 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 98.95 0.10 /workspace/coverage/default/1.spi_device_extreme_fifo_size.4079768477
97.43 0.01 99.14 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 99.05 0.10 /workspace/coverage/default/11.spi_device_tpm_all.697905260
97.44 0.01 99.14 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 99.14 0.10 /workspace/coverage/default/16.spi_device_flash_and_tpm.3781763602
97.46 0.01 99.14 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 99.24 0.10 /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3551463391
97.47 0.01 99.14 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 99.33 0.10 /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3860221040
97.48 0.01 99.14 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.00 0.00 95.86 0.00 99.43 0.10 /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.612981345
97.50 0.01 99.16 0.02 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.02 95.86 0.00 99.48 0.05 /workspace/coverage/default/10.spi_device_extreme_fifo_size.2409572479
97.50 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.52 0.05 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3356311374
97.51 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.57 0.05 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.99704270
97.52 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.62 0.05 /workspace/coverage/default/11.spi_device_fifo_underflow_overflow.1823326302
97.52 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.67 0.05 /workspace/coverage/default/11.spi_device_flash_and_tpm.3903081124
97.53 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.71 0.05 /workspace/coverage/default/11.spi_device_txrx.4046648089
97.54 0.01 99.16 0.00 96.24 0.00 98.63 0.00 95.08 0.00 98.02 0.00 95.86 0.00 99.76 0.05 /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3481358450
97.54 0.01 99.17 0.01 96.26 0.01 98.63 0.00 95.08 0.00 98.04 0.02 95.86 0.00 99.76 0.00 /workspace/coverage/default/19.spi_device_abort.1562964389
97.55 0.01 99.18 0.01 96.26 0.00 98.63 0.00 95.08 0.00 98.05 0.02 95.86 0.00 99.76 0.00 /workspace/coverage/default/15.spi_device_flash_all.1803701827
97.55 0.01 99.18 0.01 96.26 0.00 98.63 0.00 95.08 0.00 98.07 0.02 95.86 0.00 99.76 0.00 /workspace/coverage/default/17.spi_device_mailbox.3333348361
97.55 0.01 99.18 0.00 96.28 0.03 98.63 0.00 95.08 0.00 98.07 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/11.spi_device_alert_test.4103700729
97.56 0.01 99.18 0.00 96.30 0.01 98.63 0.00 95.08 0.00 98.07 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/10.spi_device_csb_read.1785976635
97.56 0.01 99.18 0.00 96.31 0.01 98.63 0.00 95.08 0.00 98.07 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/11.spi_device_rx_async_fifo_reset.3274844669
97.56 0.01 99.18 0.00 96.32 0.01 98.63 0.00 95.08 0.00 98.07 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/11.spi_device_tx_async_fifo_reset.2084384653
97.56 0.01 99.18 0.00 96.33 0.01 98.63 0.00 95.08 0.00 98.07 0.00 95.86 0.00 99.76 0.00 /workspace/coverage/default/4.spi_device_flash_all.2449689403

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2680799240
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1261227362
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2664894378
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1168719082
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3504351941
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3780644203
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2141866366
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2016139952
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.768830119
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2033375436
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3337668685
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2681978724
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.494776205
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2286639356
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.2725251413
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3744347049
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.212220734
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3547938572
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.939624395
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4189821131
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.99099451
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2147047082
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.3865909672
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.128836293
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3181426305
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.646496266
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3699237917
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.427780185
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2279956851
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1319319024
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3874889172
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3530587574
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1290409496
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2586913665
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2738063554
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1302717235
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.294027330
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1795439779
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.2063342090
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4031751588
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2940393789
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.429333003
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4119960257
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.446731048
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.907142514
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.824937074
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2672922860
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1481334067
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2795766565
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.967658944
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.2862927368
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2283981911
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1501367580
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2730353285
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2742029601
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2265514309
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.3529981634
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.935789834
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4089573479
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2144207073
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2929024463
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.276939487
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.3464602811
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.332706651
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3899836265
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1054087524
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3932867973
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3107819569
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.3987402819
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4012305404
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.195922463
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3544826775
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2149660639
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4200801152
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3954367918
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2715483005
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1978721098
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.214912655
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.660199456
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.516609649
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.849485423
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2979922449
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2331271593
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.1510490177
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2430601171
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2348402144
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3876484190
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2408066775
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1954663071
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.414833888
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.2668237901
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.4136987153
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.808873870
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.354794918
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.1276404342
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.3728524201
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.990994957
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.3132207960
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.3677699552
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.855641729
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2617876782
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.815833485
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1024660175
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1609021844
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.2371416654
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/workspace/coverage/default/7.spi_device_extreme_fifo_size.989014038
/workspace/coverage/default/7.spi_device_fifo_full.928227504
/workspace/coverage/default/7.spi_device_fifo_underflow_overflow.3228839714
/workspace/coverage/default/7.spi_device_flash_all.579650255
/workspace/coverage/default/7.spi_device_flash_and_tpm.1725182513
/workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.728160159
/workspace/coverage/default/7.spi_device_flash_mode.2906247003
/workspace/coverage/default/7.spi_device_intercept.354835864
/workspace/coverage/default/7.spi_device_intr.139958533
/workspace/coverage/default/7.spi_device_mailbox.1611964527
/workspace/coverage/default/7.spi_device_mem_parity.186609854
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1372041411
/workspace/coverage/default/7.spi_device_pass_cmd_filtering.812954830
/workspace/coverage/default/7.spi_device_perf.594939807
/workspace/coverage/default/7.spi_device_ram_cfg.2023262047
/workspace/coverage/default/7.spi_device_read_buffer_direct.3541069133
/workspace/coverage/default/7.spi_device_rx_async_fifo_reset.207785094
/workspace/coverage/default/7.spi_device_rx_timeout.410764100
/workspace/coverage/default/7.spi_device_smoke.533156232
/workspace/coverage/default/7.spi_device_stress_all.1683344324
/workspace/coverage/default/7.spi_device_tpm_all.3072723101
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3845599797
/workspace/coverage/default/7.spi_device_tpm_rw.780670021
/workspace/coverage/default/7.spi_device_tpm_sts_read.4067070788
/workspace/coverage/default/7.spi_device_tx_async_fifo_reset.4156985215
/workspace/coverage/default/7.spi_device_txrx.757651899
/workspace/coverage/default/7.spi_device_upload.3599729383
/workspace/coverage/default/8.spi_device_abort.3926083350
/workspace/coverage/default/8.spi_device_alert_test.1499077847
/workspace/coverage/default/8.spi_device_bit_transfer.2757869538
/workspace/coverage/default/8.spi_device_byte_transfer.2042202644
/workspace/coverage/default/8.spi_device_cfg_cmd.3623445648
/workspace/coverage/default/8.spi_device_csb_read.90305130
/workspace/coverage/default/8.spi_device_dummy_item_extra_dly.3519007642
/workspace/coverage/default/8.spi_device_extreme_fifo_size.3254530344
/workspace/coverage/default/8.spi_device_fifo_full.652046560
/workspace/coverage/default/8.spi_device_fifo_underflow_overflow.4119239168
/workspace/coverage/default/8.spi_device_flash_and_tpm.1592495076
/workspace/coverage/default/8.spi_device_flash_mode.1674769402
/workspace/coverage/default/8.spi_device_intercept.158591701
/workspace/coverage/default/8.spi_device_intr.2124644536
/workspace/coverage/default/8.spi_device_mailbox.1255842757
/workspace/coverage/default/8.spi_device_mem_parity.2111667679
/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.525504573
/workspace/coverage/default/8.spi_device_pass_cmd_filtering.2818124650
/workspace/coverage/default/8.spi_device_perf.2983037552
/workspace/coverage/default/8.spi_device_ram_cfg.3702095971
/workspace/coverage/default/8.spi_device_read_buffer_direct.2731859106
/workspace/coverage/default/8.spi_device_rx_async_fifo_reset.3765947491
/workspace/coverage/default/8.spi_device_rx_timeout.2440573514
/workspace/coverage/default/8.spi_device_smoke.2663021449
/workspace/coverage/default/8.spi_device_stress_all.3253811613
/workspace/coverage/default/8.spi_device_tpm_all.4271104354
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3787205637
/workspace/coverage/default/8.spi_device_tpm_rw.1514587584
/workspace/coverage/default/8.spi_device_tpm_sts_read.4271779064
/workspace/coverage/default/8.spi_device_tx_async_fifo_reset.147583798
/workspace/coverage/default/8.spi_device_txrx.2391482555
/workspace/coverage/default/8.spi_device_upload.1865004831
/workspace/coverage/default/9.spi_device_abort.3971156964
/workspace/coverage/default/9.spi_device_alert_test.2701864618
/workspace/coverage/default/9.spi_device_bit_transfer.1452099891
/workspace/coverage/default/9.spi_device_byte_transfer.860937294
/workspace/coverage/default/9.spi_device_cfg_cmd.4272698006
/workspace/coverage/default/9.spi_device_csb_read.4230362201
/workspace/coverage/default/9.spi_device_dummy_item_extra_dly.103834242
/workspace/coverage/default/9.spi_device_extreme_fifo_size.2162246379
/workspace/coverage/default/9.spi_device_fifo_full.1552452925
/workspace/coverage/default/9.spi_device_fifo_underflow_overflow.273988210
/workspace/coverage/default/9.spi_device_flash_all.2345762863
/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3249924534
/workspace/coverage/default/9.spi_device_flash_mode.1653361765
/workspace/coverage/default/9.spi_device_intercept.52216754
/workspace/coverage/default/9.spi_device_intr.154163277
/workspace/coverage/default/9.spi_device_mailbox.3994866183
/workspace/coverage/default/9.spi_device_mem_parity.2714890566
/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2597157758
/workspace/coverage/default/9.spi_device_pass_cmd_filtering.652952117
/workspace/coverage/default/9.spi_device_perf.3116111763
/workspace/coverage/default/9.spi_device_ram_cfg.3182840679
/workspace/coverage/default/9.spi_device_read_buffer_direct.1568190725
/workspace/coverage/default/9.spi_device_rx_async_fifo_reset.166649271
/workspace/coverage/default/9.spi_device_rx_timeout.3457674714
/workspace/coverage/default/9.spi_device_smoke.1909349006
/workspace/coverage/default/9.spi_device_stress_all.2304773680
/workspace/coverage/default/9.spi_device_tpm_all.3868775045
/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1569886157
/workspace/coverage/default/9.spi_device_tpm_rw.538311420
/workspace/coverage/default/9.spi_device_tpm_sts_read.419059727
/workspace/coverage/default/9.spi_device_tx_async_fifo_reset.2294050543
/workspace/coverage/default/9.spi_device_txrx.1023615438
/workspace/coverage/default/9.spi_device_upload.2585502478



Total test records in report: 1782
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/44.spi_device_perf.2487345482 Jan 03 02:01:52 PM PST 24 Jan 03 02:05:25 PM PST 24 16492994823 ps
T4 /workspace/coverage/default/6.spi_device_cfg_cmd.2156728121 Jan 03 01:51:52 PM PST 24 Jan 03 01:52:10 PM PST 24 881087721 ps
T2 /workspace/coverage/default/0.spi_device_byte_transfer.2101143146 Jan 03 01:50:11 PM PST 24 Jan 03 01:50:35 PM PST 24 436449874 ps
T3 /workspace/coverage/default/34.spi_device_stress_all.150578607 Jan 03 02:01:20 PM PST 24 Jan 03 02:08:43 PM PST 24 400043776989 ps
T13 /workspace/coverage/default/18.spi_device_tpm_all.3284860481 Jan 03 01:57:19 PM PST 24 Jan 03 01:57:45 PM PST 24 9662846839 ps
T7 /workspace/coverage/default/32.spi_device_dummy_item_extra_dly.2413594227 Jan 03 01:59:36 PM PST 24 Jan 03 02:08:32 PM PST 24 99986804237 ps
T9 /workspace/coverage/default/29.spi_device_mailbox.1884775031 Jan 03 01:58:34 PM PST 24 Jan 03 01:59:01 PM PST 24 5371648087 ps
T69 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.824937074 Jan 03 01:29:57 PM PST 24 Jan 03 01:30:55 PM PST 24 1100082352 ps
T70 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3181426305 Jan 03 01:29:22 PM PST 24 Jan 03 01:29:37 PM PST 24 115590795 ps
T71 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1711600861 Jan 03 01:29:52 PM PST 24 Jan 03 01:30:41 PM PST 24 2796460756 ps
T76 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3728524201 Jan 03 01:29:55 PM PST 24 Jan 03 01:30:39 PM PST 24 25908042 ps
T77 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1253654661 Jan 03 01:30:01 PM PST 24 Jan 03 01:30:53 PM PST 24 41331270 ps
T78 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2317922176 Jan 03 01:28:43 PM PST 24 Jan 03 01:28:52 PM PST 24 14929739 ps
T72 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.99099451 Jan 03 01:29:24 PM PST 24 Jan 03 01:29:38 PM PST 24 36364447 ps
T79 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3337001521 Jan 03 01:30:05 PM PST 24 Jan 03 01:30:58 PM PST 24 13973207 ps
T97 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3514657789 Jan 03 01:28:56 PM PST 24 Jan 03 01:29:01 PM PST 24 18772921 ps
T95 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3651852925 Jan 03 01:28:11 PM PST 24 Jan 03 01:28:22 PM PST 24 61338997 ps
T96 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.49243871 Jan 03 01:28:14 PM PST 24 Jan 03 01:28:28 PM PST 24 176518731 ps
T130 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2033375436 Jan 03 01:28:09 PM PST 24 Jan 03 01:28:37 PM PST 24 1253505423 ps
T73 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4271862632 Jan 03 01:28:45 PM PST 24 Jan 03 01:28:58 PM PST 24 699062107 ps
T169 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3017297675 Jan 03 01:28:09 PM PST 24 Jan 03 01:28:21 PM PST 24 312019782 ps
T171 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4031751588 Jan 03 01:29:54 PM PST 24 Jan 03 01:30:34 PM PST 24 397827272 ps
T74 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3554536885 Jan 03 01:28:10 PM PST 24 Jan 03 01:28:27 PM PST 24 860128433 ps
T98 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2257430650 Jan 03 01:30:06 PM PST 24 Jan 03 01:31:00 PM PST 24 16015213 ps
T99 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3987493322 Jan 03 01:28:05 PM PST 24 Jan 03 01:28:16 PM PST 24 22332201 ps
T170 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2681978724 Jan 03 01:28:13 PM PST 24 Jan 03 01:28:52 PM PST 24 7820674336 ps
T172 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1295488528 Jan 03 01:30:02 PM PST 24 Jan 03 01:30:53 PM PST 24 29879759 ps
T173 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1157386988 Jan 03 01:30:00 PM PST 24 Jan 03 01:30:52 PM PST 24 51373955 ps
T158 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1371977896 Jan 03 01:28:10 PM PST 24 Jan 03 01:28:21 PM PST 24 16152134 ps
T159 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2337025657 Jan 03 01:28:13 PM PST 24 Jan 03 01:28:26 PM PST 24 22668622 ps
T134 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.429333003 Jan 03 01:29:52 PM PST 24 Jan 03 01:30:37 PM PST 24 2947850215 ps
T160 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1168719082 Jan 03 01:28:11 PM PST 24 Jan 03 01:28:22 PM PST 24 20416988 ps
T161 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3932867973 Jan 03 01:29:56 PM PST 24 Jan 03 01:30:44 PM PST 24 43441518 ps
T135 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2062204787 Jan 03 01:28:08 PM PST 24 Jan 03 01:28:24 PM PST 24 4293194113 ps
T165 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.212220734 Jan 03 01:28:12 PM PST 24 Jan 03 01:28:40 PM PST 24 1393313528 ps
T136 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.939624395 Jan 03 01:28:10 PM PST 24 Jan 03 01:28:23 PM PST 24 128233171 ps
T168 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2001105419 Jan 03 01:28:13 PM PST 24 Jan 03 01:28:29 PM PST 24 877410380 ps
T142 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.768830119 Jan 03 01:28:11 PM PST 24 Jan 03 01:28:23 PM PST 24 311777205 ps
T197 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.99704270 Jan 03 01:29:24 PM PST 24 Jan 03 01:29:37 PM PST 24 15139177 ps
T207 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3891200818 Jan 03 01:29:00 PM PST 24 Jan 03 01:29:07 PM PST 24 40258659 ps
T174 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.516609649 Jan 03 01:28:06 PM PST 24 Jan 03 01:28:43 PM PST 24 5544127850 ps
T395 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2617876782 Jan 03 01:28:09 PM PST 24 Jan 03 01:28:31 PM PST 24 820153236 ps
T394 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2929024463 Jan 03 01:29:21 PM PST 24 Jan 03 01:29:35 PM PST 24 23859768 ps
T206 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2550378332 Jan 03 01:30:00 PM PST 24 Jan 03 01:30:51 PM PST 24 31090286 ps
T175 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3780644203 Jan 03 01:28:09 PM PST 24 Jan 03 01:28:23 PM PST 24 204977250 ps
T162 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.646496266 Jan 03 01:29:46 PM PST 24 Jan 03 01:30:22 PM PST 24 996742089 ps
T137 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.630767978 Jan 03 01:28:13 PM PST 24 Jan 03 01:28:28 PM PST 24 685293510 ps
T166 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1054087524 Jan 03 01:28:44 PM PST 24 Jan 03 01:28:58 PM PST 24 110856609 ps
T208 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.354794918 Jan 03 01:29:53 PM PST 24 Jan 03 01:30:32 PM PST 24 23296485 ps
T396 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3529981634 Jan 03 01:29:03 PM PST 24 Jan 03 01:29:09 PM PST 24 11612186 ps
T167 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2012759961 Jan 03 01:28:11 PM PST 24 Jan 03 01:28:35 PM PST 24 435427959 ps
T192 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1954663071 Jan 03 01:28:07 PM PST 24 Jan 03 01:28:25 PM PST 24 947842951 ps
T176 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.967658944 Jan 03 01:28:43 PM PST 24 Jan 03 01:28:53 PM PST 24 188258356 ps
T163 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2759548167 Jan 03 01:28:11 PM PST 24 Jan 03 01:28:44 PM PST 24 12090138823 ps
T397 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3918757191 Jan 03 01:28:10 PM PST 24 Jan 03 01:28:21 PM PST 24 52739636 ps
T398 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.345329335 Jan 03 01:28:44 PM PST 24 Jan 03 01:28:52 PM PST 24 51266635 ps
T399 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1662456606 Jan 03 01:28:57 PM PST 24 Jan 03 01:29:03 PM PST 24 185821258 ps
T400 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2126712683 Jan 03 01:28:13 PM PST 24 Jan 03 01:28:25 PM PST 24 100391498 ps
T401 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2283981911 Jan 03 01:29:56 PM PST 24 Jan 03 01:30:47 PM PST 24 65940597 ps
T193 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4119960257 Jan 03 01:30:00 PM PST 24 Jan 03 01:30:53 PM PST 24 152388581 ps
T402 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3987402819 Jan 03 01:28:59 PM PST 24 Jan 03 01:29:05 PM PST 24 52378179 ps
T177 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1206919266 Jan 03 01:28:08 PM PST 24 Jan 03 01:28:20 PM PST 24 20155570 ps
T194 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2866398330 Jan 03 01:28:11 PM PST 24 Jan 03 01:28:24 PM PST 24 171941042 ps
T178 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1795439779 Jan 03 01:29:34 PM PST 24 Jan 03 01:29:54 PM PST 24 31005688 ps
T403 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.907142514 Jan 03 01:29:55 PM PST 24 Jan 03 01:30:40 PM PST 24 12238842 ps
T404 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2429716149 Jan 03 01:29:13 PM PST 24 Jan 03 01:29:21 PM PST 24 36193882 ps
T195 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3547938572 Jan 03 01:28:08 PM PST 24 Jan 03 01:28:22 PM PST 24 621319314 ps
T196 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2738063554 Jan 03 01:29:25 PM PST 24 Jan 03 01:29:40 PM PST 24 160354631 ps
T138 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1302717235 Jan 03 01:29:52 PM PST 24 Jan 03 01:30:27 PM PST 24 367853555 ps
T405 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2331271593 Jan 03 01:28:07 PM PST 24 Jan 03 01:28:18 PM PST 24 140982974 ps
T406 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4200801152 Jan 03 01:29:43 PM PST 24 Jan 03 01:29:57 PM PST 24 36539637 ps
T179 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1328841792 Jan 03 01:28:11 PM PST 24 Jan 03 01:28:23 PM PST 24 38171165 ps
T407 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3962443393 Jan 03 01:28:12 PM PST 24 Jan 03 01:28:46 PM PST 24 389270543 ps
T164 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4168021126 Jan 03 01:28:14 PM PST 24 Jan 03 01:28:33 PM PST 24 299272394 ps
T408 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.862285823 Jan 03 01:28:09 PM PST 24 Jan 03 01:28:21 PM PST 24 81123512 ps
T409 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.385282342 Jan 03 01:28:12 PM PST 24 Jan 03 01:28:25 PM PST 24 73828132 ps
T410 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2348402144 Jan 03 01:28:08 PM PST 24 Jan 03 01:28:29 PM PST 24 5503207587 ps
T411 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2279956851 Jan 03 01:29:24 PM PST 24 Jan 03 01:29:38 PM PST 24 87776821 ps
T412 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3337668685 Jan 03 01:28:08 PM PST 24 Jan 03 01:28:27 PM PST 24 525301025 ps
T180 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.276939487 Jan 03 01:29:13 PM PST 24 Jan 03 01:29:23 PM PST 24 126163630 ps
T413 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2063342090 Jan 03 01:29:33 PM PST 24 Jan 03 01:29:52 PM PST 24 14413758 ps
T181 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3744347049 Jan 03 01:28:14 PM PST 24 Jan 03 01:28:32 PM PST 24 1078892087 ps
T141 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2686726606 Jan 03 01:28:42 PM PST 24 Jan 03 01:28:52 PM PST 24 22420875 ps
T414 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1261227362 Jan 03 01:28:10 PM PST 24 Jan 03 01:29:02 PM PST 24 11896702239 ps
T415 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3874889172 Jan 03 01:29:24 PM PST 24 Jan 03 01:29:52 PM PST 24 6438022337 ps
T139 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.737750458 Jan 03 01:28:13 PM PST 24 Jan 03 01:28:31 PM PST 24 414931775 ps
T416 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3482956635 Jan 03 01:28:10 PM PST 24 Jan 03 01:28:30 PM PST 24 135206055 ps
T417 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1339871233 Jan 03 01:30:05 PM PST 24 Jan 03 01:30:59 PM PST 24 43447010 ps
T140 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2863292236 Jan 03 01:28:11 PM PST 24 Jan 03 01:28:25 PM PST 24 54451581 ps
T418 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2664894378 Jan 03 01:28:10 PM PST 24 Jan 03 01:28:22 PM PST 24 87278997 ps
T419 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1118489600 Jan 03 01:28:59 PM PST 24 Jan 03 01:29:06 PM PST 24 462741008 ps
T420 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3865909672 Jan 03 01:29:48 PM PST 24 Jan 03 01:30:04 PM PST 24 18551907 ps
T421 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2144207073 Jan 03 01:28:43 PM PST 24 Jan 03 01:29:00 PM PST 24 1508389321 ps
T422 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2715483005 Jan 03 01:29:46 PM PST 24 Jan 03 01:30:03 PM PST 24 101172638 ps
T423 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2265514309 Jan 03 01:28:55 PM PST 24 Jan 03 01:29:01 PM PST 24 592065715 ps
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T425 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3699237917 Jan 03 01:29:20 PM PST 24 Jan 03 01:29:33 PM PST 24 33736208 ps
T426 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.414833888 Jan 03 01:29:54 PM PST 24 Jan 03 01:30:33 PM PST 24 17228803 ps
T427 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1162035107 Jan 03 01:28:59 PM PST 24 Jan 03 01:29:07 PM PST 24 536664680 ps
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T429 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2371416654 Jan 03 01:28:05 PM PST 24 Jan 03 01:28:17 PM PST 24 43896182 ps
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T455 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2742029601 Jan 03 01:29:17 PM PST 24 Jan 03 01:29:31 PM PST 24 68793746 ps
T456 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4080486759 Jan 03 01:28:46 PM PST 24 Jan 03 01:28:54 PM PST 24 52930130 ps
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T458 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2862927368 Jan 03 01:29:54 PM PST 24 Jan 03 01:30:34 PM PST 24 89592274 ps
T217 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2730353285 Jan 03 01:29:55 PM PST 24 Jan 03 01:30:59 PM PST 24 1293546842 ps
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T463 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.294027330 Jan 03 01:29:59 PM PST 24 Jan 03 01:30:52 PM PST 24 30644842 ps
T464 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2398587501 Jan 03 01:28:10 PM PST 24 Jan 03 01:28:26 PM PST 24 526411710 ps
T465 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2149660639 Jan 03 01:29:23 PM PST 24 Jan 03 01:29:36 PM PST 24 19574023 ps
T466 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1481334067 Jan 03 01:29:54 PM PST 24 Jan 03 01:30:50 PM PST 24 412038475 ps
T467 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1276404342 Jan 03 01:29:55 PM PST 24 Jan 03 01:30:39 PM PST 24 33662183 ps
T468 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.904922672 Jan 03 01:29:57 PM PST 24 Jan 03 01:30:50 PM PST 24 30554840 ps
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T470 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.208766377 Jan 03 01:29:55 PM PST 24 Jan 03 01:30:38 PM PST 24 15160516 ps
T218 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.62701057 Jan 03 01:29:00 PM PST 24 Jan 03 01:29:15 PM PST 24 1155039141 ps
T471 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3653669705 Jan 03 01:29:00 PM PST 24 Jan 03 01:29:08 PM PST 24 164859697 ps
T472 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.494776205 Jan 03 01:28:13 PM PST 24 Jan 03 01:28:26 PM PST 24 244661405 ps
T473 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2286639356 Jan 03 01:28:13 PM PST 24 Jan 03 01:28:27 PM PST 24 1240092232 ps
T474 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.214912655 Jan 03 01:29:50 PM PST 24 Jan 03 01:30:23 PM PST 24 565527780 ps
T475 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.25213357 Jan 03 01:28:09 PM PST 24 Jan 03 01:28:23 PM PST 24 200584112 ps
T476 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4089573479 Jan 03 01:28:58 PM PST 24 Jan 03 01:29:05 PM PST 24 242020605 ps
T477 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.446731048 Jan 03 01:29:53 PM PST 24 Jan 03 01:30:30 PM PST 24 206940916 ps
T478 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2612619770 Jan 03 01:28:12 PM PST 24 Jan 03 01:28:24 PM PST 24 12614185 ps
T479 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1978721098 Jan 03 01:29:47 PM PST 24 Jan 03 01:30:06 PM PST 24 126232934 ps
T480 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.128836293 Jan 03 01:29:22 PM PST 24 Jan 03 01:29:36 PM PST 24 239546298 ps
T481 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1501367580 Jan 03 01:29:55 PM PST 24 Jan 03 01:30:40 PM PST 24 112934654 ps
T482 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2016139952 Jan 03 01:28:11 PM PST 24 Jan 03 01:28:26 PM PST 24 904384844 ps
T483 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3954367918 Jan 03 01:29:24 PM PST 24 Jan 03 01:29:37 PM PST 24 42021962 ps
T484 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3641630508 Jan 03 01:29:22 PM PST 24 Jan 03 01:29:36 PM PST 24 1217274246 ps
T485 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.935789834 Jan 03 01:28:59 PM PST 24 Jan 03 01:29:09 PM PST 24 768383099 ps
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T487 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1319319024 Jan 03 01:29:12 PM PST 24 Jan 03 01:29:20 PM PST 24 178460267 ps
T488 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.837956888 Jan 03 01:30:05 PM PST 24 Jan 03 01:31:00 PM PST 24 174528582 ps
T489 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4101610613 Jan 03 01:28:10 PM PST 24 Jan 03 01:28:27 PM PST 24 320283395 ps
T490 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2147047082 Jan 03 01:29:24 PM PST 24 Jan 03 01:29:38 PM PST 24 65562715 ps
T491 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1510490177 Jan 03 01:28:08 PM PST 24 Jan 03 01:28:18 PM PST 24 24596590 ps
T492 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.919139379 Jan 03 01:29:13 PM PST 24 Jan 03 01:29:20 PM PST 24 77066050 ps
T493 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.808873870 Jan 03 01:29:52 PM PST 24 Jan 03 01:30:26 PM PST 24 18873431 ps
T494 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2725251413 Jan 03 01:28:11 PM PST 24 Jan 03 01:28:21 PM PST 24 11953694 ps
T495 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3504351941 Jan 03 01:28:10 PM PST 24 Jan 03 01:28:21 PM PST 24 44960262 ps
T496 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3107819569 Jan 03 01:29:24 PM PST 24 Jan 03 01:29:38 PM PST 24 681193880 ps
T497 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.359581066 Jan 03 01:28:55 PM PST 24 Jan 03 01:29:05 PM PST 24 1055935840 ps
T498 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.332706651 Jan 03 01:28:58 PM PST 24 Jan 03 01:29:05 PM PST 24 115082654 ps
T499 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2795766565 Jan 03 01:29:57 PM PST 24 Jan 03 01:30:52 PM PST 24 35910745 ps
T500 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4136987153 Jan 03 01:29:52 PM PST 24 Jan 03 01:30:26 PM PST 24 114091740 ps
T501 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3677699552 Jan 03 01:29:57 PM PST 24 Jan 03 01:30:51 PM PST 24 33726409 ps
T502 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3988242602 Jan 03 01:28:58 PM PST 24 Jan 03 01:29:04 PM PST 24 53896358 ps
T503 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1539908661 Jan 03 01:30:05 PM PST 24 Jan 03 01:30:57 PM PST 24 12908887 ps
T504 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1609021844 Jan 03 01:28:10 PM PST 24 Jan 03 01:28:22 PM PST 24 38828640 ps
T505 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1024660175 Jan 03 01:28:09 PM PST 24 Jan 03 01:28:21 PM PST 24 40439922 ps
T506 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2768578865 Jan 03 01:30:02 PM PST 24 Jan 03 01:30:53 PM PST 24 15454043 ps
T507 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3511956439 Jan 03 01:28:44 PM PST 24 Jan 03 01:28:59 PM PST 24 276474266 ps
T42 /workspace/coverage/default/19.spi_device_abort.1562964389 Jan 03 01:57:25 PM PST 24 Jan 03 01:57:34 PM PST 24 26763678 ps
T12 /workspace/coverage/default/39.spi_device_byte_transfer.3403834408 Jan 03 02:00:49 PM PST 24 Jan 03 02:01:03 PM PST 24 470821486 ps
T10 /workspace/coverage/default/26.spi_device_flash_mode.4236370257 Jan 03 01:58:34 PM PST 24 Jan 03 01:58:56 PM PST 24 26763141411 ps
T11 /workspace/coverage/default/28.spi_device_intercept.1940612256 Jan 03 01:58:45 PM PST 24 Jan 03 01:59:06 PM PST 24 4370593714 ps
T8 /workspace/coverage/default/48.spi_device_extreme_fifo_size.365311632 Jan 03 02:03:27 PM PST 24 Jan 03 02:18:04 PM PST 24 62297843424 ps
T19 /workspace/coverage/default/45.spi_device_cfg_cmd.971075797 Jan 03 02:02:52 PM PST 24 Jan 03 02:03:07 PM PST 24 237364067 ps
T14 /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3551463391 Jan 03 01:58:28 PM PST 24 Jan 03 01:58:39 PM PST 24 6423018031 ps
T31 /workspace/coverage/default/23.spi_device_tpm_sts_read.565771209 Jan 03 01:58:02 PM PST 24 Jan 03 01:58:05 PM PST 24 218248807 ps
T32 /workspace/coverage/default/15.spi_device_extreme_fifo_size.1791385464 Jan 03 01:56:38 PM PST 24 Jan 03 02:29:05 PM PST 24 179490712931 ps
T33 /workspace/coverage/default/6.spi_device_smoke.1597015099 Jan 03 01:51:22 PM PST 24 Jan 03 01:51:34 PM PST 24 48524802 ps
T34 /workspace/coverage/default/9.spi_device_byte_transfer.860937294 Jan 03 01:54:37 PM PST 24 Jan 03 01:54:44 PM PST 24 391977018 ps
T35 /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.305007949 Jan 03 02:03:17 PM PST 24 Jan 03 02:03:57 PM PST 24 8465506052 ps
T90 /workspace/coverage/default/3.spi_device_csb_read.380462756 Jan 03 01:51:28 PM PST 24 Jan 03 01:51:50 PM PST 24 17626475 ps
T5 /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.772658494 Jan 03 01:58:32 PM PST 24 Jan 03 02:07:49 PM PST 24 612697095610 ps
T6 /workspace/coverage/default/21.spi_device_flash_all.81078064 Jan 03 01:58:06 PM PST 24 Jan 03 01:59:03 PM PST 24 3319130799 ps
T36 /workspace/coverage/default/17.spi_device_perf.3457641714 Jan 03 01:57:25 PM PST 24 Jan 03 02:02:32 PM PST 24 70639283668 ps
T18 /workspace/coverage/default/1.spi_device_intercept.2166021953 Jan 03 01:50:11 PM PST 24 Jan 03 01:50:38 PM PST 24 700537412 ps
T37 /workspace/coverage/default/9.spi_device_read_buffer_direct.1568190725 Jan 03 01:54:34 PM PST 24 Jan 03 01:54:42 PM PST 24 674109813 ps
T46 /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2337833172 Jan 03 01:57:00 PM PST 24 Jan 03 01:57:22 PM PST 24 11687993328 ps
T15 /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1372958921 Jan 03 01:54:41 PM PST 24 Jan 03 02:00:35 PM PST 24 145417530596 ps
T224 /workspace/coverage/default/22.spi_device_smoke.2957440064 Jan 03 01:58:36 PM PST 24 Jan 03 01:58:46 PM PST 24 97285160 ps
T16 /workspace/coverage/default/32.spi_device_intercept.2948428230 Jan 03 01:59:38 PM PST 24 Jan 03 01:59:56 PM PST 24 5383379023 ps
T91 /workspace/coverage/default/34.spi_device_csb_read.776165523 Jan 03 02:00:20 PM PST 24 Jan 03 02:00:29 PM PST 24 15617729 ps
T17 /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.612981345 Jan 03 01:52:29 PM PST 24 Jan 03 01:54:41 PM PST 24 14238410115 ps
T222 /workspace/coverage/default/26.spi_device_byte_transfer.597001905 Jan 03 01:58:34 PM PST 24 Jan 03 01:58:41 PM PST 24 371822642 ps
T184 /workspace/coverage/default/42.spi_device_bit_transfer.902096832 Jan 03 02:01:29 PM PST 24 Jan 03 02:01:46 PM PST 24 316431908 ps
T83 /workspace/coverage/default/47.spi_device_extreme_fifo_size.1859938288 Jan 03 02:02:57 PM PST 24 Jan 03 02:13:42 PM PST 24 983714325314 ps
T113 /workspace/coverage/default/42.spi_device_tpm_all.2878746460 Jan 03 02:01:40 PM PST 24 Jan 03 02:03:48 PM PST 24 86052978520 ps
T38 /workspace/coverage/default/44.spi_device_read_buffer_direct.289827451 Jan 03 02:01:46 PM PST 24 Jan 03 02:02:09 PM PST 24 1438414334 ps
T182 /workspace/coverage/default/48.spi_device_stress_all.3769556690 Jan 03 02:03:30 PM PST 24 Jan 03 02:27:13 PM PST 24 248117522256 ps
T183 /workspace/coverage/default/10.spi_device_txrx.4227333188 Jan 03 01:54:35 PM PST 24 Jan 03 01:58:09 PM PST 24 19728730162 ps
T114 /workspace/coverage/default/29.spi_device_tpm_sts_read.1268726103 Jan 03 01:58:35 PM PST 24 Jan 03 01:58:41 PM PST 24 27952230 ps
T115 /workspace/coverage/default/9.spi_device_tpm_all.3868775045 Jan 03 01:54:35 PM PST 24 Jan 03 01:54:43 PM PST 24 670209979 ps
T84 /workspace/coverage/default/14.spi_device_tx_async_fifo_reset.2023621244 Jan 03 01:56:19 PM PST 24 Jan 03 01:56:31 PM PST 24 31224171 ps
T21 /workspace/coverage/default/39.spi_device_upload.3320651552 Jan 03 02:01:24 PM PST 24 Jan 03 02:01:47 PM PST 24 7523430904 ps
T155 /workspace/coverage/default/20.spi_device_perf.2419626759 Jan 03 01:57:27 PM PST 24 Jan 03 02:09:46 PM PST 24 28879185296 ps
T156 /workspace/coverage/default/48.spi_device_perf.1005820054 Jan 03 02:03:38 PM PST 24 Jan 03 02:15:47 PM PST 24 32967049817 ps
T43 /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3047809397 Jan 03 01:57:46 PM PST 24 Jan 03 02:00:47 PM PST 24 109347194198 ps
T157 /workspace/coverage/default/13.spi_device_txrx.701056825 Jan 03 01:56:16 PM PST 24 Jan 03 02:07:37 PM PST 24 78616284916 ps
T47 /workspace/coverage/default/10.spi_device_extreme_fifo_size.2409572479 Jan 03 01:54:36 PM PST 24 Jan 03 02:08:27 PM PST 24 119857540777 ps
T223 /workspace/coverage/default/41.spi_device_smoke.554543822 Jan 03 02:00:42 PM PST 24 Jan 03 02:00:56 PM PST 24 200857054 ps
T324 /workspace/coverage/default/30.spi_device_intercept.2349727487 Jan 03 01:59:31 PM PST 24 Jan 03 01:59:39 PM PST 24 1340025004 ps
T508 /workspace/coverage/default/44.spi_device_csb_read.2029087581 Jan 03 02:01:47 PM PST 24 Jan 03 02:02:06 PM PST 24 55667977 ps
T118 /workspace/coverage/default/23.spi_device_intr.819192811 Jan 03 01:57:50 PM PST 24 Jan 03 01:58:20 PM PST 24 12960626042 ps
T119 /workspace/coverage/default/39.spi_device_intr.3050808023 Jan 03 02:00:27 PM PST 24 Jan 03 02:01:10 PM PST 24 4098685616 ps
T100 /workspace/coverage/default/19.spi_device_ram_cfg.1934632928 Jan 03 01:57:23 PM PST 24 Jan 03 01:57:30 PM PST 24 20988119 ps
T307 /workspace/coverage/default/29.spi_device_cfg_cmd.2659631561 Jan 03 01:58:42 PM PST 24 Jan 03 01:59:00 PM PST 24 484709613 ps
T92 /workspace/coverage/default/35.spi_device_alert_test.356206052 Jan 03 02:00:19 PM PST 24 Jan 03 02:00:27 PM PST 24 25289398 ps
T304 /workspace/coverage/default/43.spi_device_perf.1411979743 Jan 03 02:01:32 PM PST 24 Jan 03 02:17:14 PM PST 24 44706454790 ps
T120 /workspace/coverage/default/41.spi_device_intr.3718896786 Jan 03 02:00:50 PM PST 24 Jan 03 02:02:00 PM PST 24 28729725245 ps
T116 /workspace/coverage/default/11.spi_device_tpm_all.697905260 Jan 03 01:54:41 PM PST 24 Jan 03 01:55:49 PM PST 24 3666451387 ps
T23 /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3520535689 Jan 03 01:51:27 PM PST 24 Jan 03 01:51:55 PM PST 24 7315567564 ps
T220 /workspace/coverage/default/10.spi_device_dummy_item_extra_dly.1617596895 Jan 03 01:54:36 PM PST 24 Jan 03 02:02:58 PM PST 24 103353663008 ps
T219 /workspace/coverage/default/43.spi_device_dummy_item_extra_dly.264995356 Jan 03 02:01:29 PM PST 24 Jan 03 02:03:45 PM PST 24 56935255155 ps
T221 /workspace/coverage/default/9.spi_device_bit_transfer.1452099891 Jan 03 01:54:36 PM PST 24 Jan 03 01:54:44 PM PST 24 183006140 ps
T509 /workspace/coverage/default/46.spi_device_byte_transfer.3485886950 Jan 03 02:03:13 PM PST 24 Jan 03 02:03:26 PM PST 24 142255504 ps
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T225 /workspace/coverage/default/19.spi_device_bit_transfer.951169860 Jan 03 01:57:20 PM PST 24 Jan 03 01:57:27 PM PST 24 1129108718 ps
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T87 /workspace/coverage/default/36.spi_device_rx_async_fifo_reset.4036859865 Jan 03 02:01:22 PM PST 24 Jan 03 02:01:39 PM PST 24 68187561 ps
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T148 /workspace/coverage/default/8.spi_device_cfg_cmd.3623445648 Jan 03 01:52:09 PM PST 24 Jan 03 01:52:28 PM PST 24 8873401909 ps
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