Group : spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg
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Group : spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 16 0 16 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_bit_order 2 0 2 100.00 100 1 1 2
cp_cpha 2 0 2 100.00 100 1 1 2
cp_cpol 2 0 2 100.00 100 1 1 2
cp_rx_order 2 0 2 100.00 100 1 1 2
rx_order 2 0 2 100.00 100 1 1 2
tx_order 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_bit_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bit_order

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3143542 1 T1 8292 T2 48 T3 4533
auto[1] 3062600 1 T1 4814 T7 10416 T8 1589


Summary for Variable cp_cpha

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_cpha

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2903752 1 T2 48 T3 2172 T7 5849
auto[1] 3302390 1 T1 13106 T3 2361 T7 4567


Summary for Variable cp_cpol

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_cpol

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3031770 1 T1 4814 T3 2172 T7 5849
auto[1] 3174372 1 T1 8292 T2 48 T3 2361


Summary for Variable cp_rx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rx_order

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3016701 1 T8 2156 T32 1865 T33 3
auto[1] 3189441 1 T1 13106 T2 48 T3 4533


Summary for Variable rx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rx_order

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3016701 1 T8 2156 T32 1865 T33 3
auto[1] 3189441 1 T1 13106 T2 48 T3 4533


Summary for Variable tx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for tx_order

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3143542 1 T1 8292 T2 48 T3 4533
auto[1] 3062600 1 T1 4814 T7 10416 T8 1589


Summary for Cross cr_all

Samples crossed: tx_order rx_order cp_cpol cp_cpha
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
tx_orderrx_ordercp_cpolcp_cphaCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] 331169 1 T8 567 T183 8923 T118 608
auto[0] auto[0] auto[0] auto[1] 440872 1 T184 4 T157 2711 T219 1638
auto[0] auto[0] auto[1] auto[0] 321655 1 T32 1167 T33 3 T184 4
auto[0] auto[0] auto[1] auto[1] 409488 1 T157 3438 T220 6049 T221 2
auto[0] auto[1] auto[0] auto[0] 306211 1 T3 2172 T36 8912 T184 4
auto[0] auto[1] auto[0] auto[1] 523441 1 T33 3 T222 54 T184 16
auto[0] auto[1] auto[1] auto[0] 384775 1 T2 48 T12 48 T182 6656
auto[0] auto[1] auto[1] auto[1] 425931 1 T1 8292 T3 2361 T184 11
auto[1] auto[0] auto[0] auto[0] 421205 1 T182 6108 T157 5943 T221 9
auto[1] auto[0] auto[0] auto[1] 303251 1 T83 825 T47 1541 T223 2
auto[1] auto[0] auto[1] auto[0] 310015 1 T8 1589 T32 698 T34 50
auto[1] auto[0] auto[1] auto[1] 479046 1 T224 5 T184 13 T182 8436
auto[1] auto[1] auto[0] auto[0] 312154 1 T7 5849 T221 5 T225 14
auto[1] auto[1] auto[0] auto[1] 393467 1 T1 4814 T184 12 T84 1
auto[1] auto[1] auto[1] auto[0] 516568 1 T36 7541 T184 6 T155 9934
auto[1] auto[1] auto[1] auto[1] 326894 1 T7 4567 T184 3 T156 10157

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