Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37176	1			T4	6		T3	434		T19	24
auto[SpiFlashAddrCfg]	7869	1			T3	97		T9	6		T10	6
auto[SpiFlashAddr3b]	9532	1			T3	126		T10	7		T11	8
auto[SpiFlashAddr4b]	7816	1			T3	94		T9	4		T10	3

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36032

1

T4

6

T3

422

T9

10

auto[1]

26361

1

T3

329

T14

32

T5

140

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33599

1

T4

6

T3

441

T9

6

auto[1]

28794

1

T3

310

T9

4

T10

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42014	1			T4	6		T3	519		T11	4
values[1]	1185	1			T3	18		T14	12		T5	11
values[2]	1562	1			T3	23		T9	4		T5	19
values[3]	1542	1			T3	20		T10	7		T14	2
values[4]	1595	1			T3	36		T5	11		T6	9
values[5]	1520	1			T3	11		T10	9		T5	16
values[6]	1447	1			T3	16		T5	16		T6	6
values[7]	1543	1			T3	9		T5	9		T6	6
values[8]	9985	1			T3	99		T9	6		T11	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28305

1

T4

6

T9

10

T11

10

auto[1]

34088

1

T3

751

T10

16

T5

401

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

60201

1

T4

6

T3

714

T9

10

write

2192

1

T3

37

T14

10

T5

21

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20337

1

T4

6

T3

238

T9

10

valids[0x1]

42056

1

T3

513

T10

4

T11

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1580	1			T3	22		T5	17		T6	8
internal_process_ops[0x5a]	1678	1			T3	22		T11	2		T5	13
internal_process_ops[0x05]	22879	1			T3	247		T5	76		T6	308
internal_process_ops[0x35]	1593	1			T3	22		T5	12		T6	10
internal_process_ops[0x15]	1720	1			T3	23		T14	2		T5	13
internal_process_ops[0x03]	1069	1			T3	7		T10	4		T11	2
internal_process_ops[0x0b]	1189	1			T3	8		T5	3		T18	2
internal_process_ops[0x3b]	1140	1			T3	3		T10	6		T5	4
internal_process_ops[0x6b]	1143	1			T3	4		T10	3		T5	1
internal_process_ops[0xbb]	1150	1			T3	7		T9	6		T10	3
internal_process_ops[0xeb]	1138	1			T3	7		T9	4		T11	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61315

1

T4

6

T3

733

T9

10

auto[1]

1078

1

T3

18

T14

10

T5

10

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60319

1

T4

6

T3

725

T9

10

auto[1]

2074

1

T3

26

T5

23

T6

16

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9774

1

T4

6

T19

24

T18

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5621

1

T14

6

T15

121

T17

114

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2036

1

T9

6

T18

2

T15

27

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1693

1

T14

12

T15

18

T17

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2481

1

T11

8

T18

12

T15

26

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1989

1

T14

4

T15

32

T17

29

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2070

1

T9

4

T11

2

T18

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1676

1

T15

32

T17

23

T132

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

66

1

T15

5

T28

3

T209

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

69

1

T20

2

T27

1

T30

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

60

1

T20

2

T27

3

T28

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

69

1

T26

1

T210

3

T211

8

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

76

1

T15

6

T17

3

T131

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

40

1

T17

5

T30

1

T212

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

49

1

T15

1

T17

1

T26

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

81

1

T14

6

T15

1

T17

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

80

1

T17

3

T26

2

T28

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

52

1

T17

1

T20

1

T28

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

37

1

T15

1

T17

2

T29

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

57

1

T17

4

T20

2

T27

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

68

1

T16

2

T213

2

T212

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

50

1

T15

2

T20

3

T26

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

59

1

T15

2

T17

1

T26

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

52

1

T14

4

T26

1

T30

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12355

1

T3

257

T5

154

T6

216

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8863

1

T3

173

T5

41

T6

187

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1941

1

T3

49

T10

6

T5

43

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1681

1

T3

37

T5

36

T6

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2402

1

T3

67

T10

7

T5

29

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2092

1

T3

52

T5

27

T6

41

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1876

1

T3

31

T10

3

T5

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1651

1

T3

48

T5

28

T6

16

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

90

1

T3

1

T5

3

T6

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

67

1

T3

1

T5

4

T43

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

77

1

T3

1

T43

1

T45

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

65

1

T3

1

T5

1

T6

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

67

1

T3

4

T43

2

T68

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

59

1

T5

2

T45

1

T214

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

65

1

T3

4

T5

1

T6

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

81

1

T3

3

T5

2

T44

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

81

1

T3

4

T5

3

T43

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

87

1

T3

1

T5

1

T6

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

83

1

T5

3

T6

1

T43

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

91

1

T3

2

T215

6

T199

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

76

1

T3

2

T43

1

T44

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

69

1

T3

5

T199

5

T216

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

80

1

T3

3

T5

1

T44

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

89

1

T3

5

T43

1

T68

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3783	1			T4	6		T19	24		T14	4
auto[0]	values[0]	valids[0x1]	14146	1			T11	4		T14	12		T18	12
auto[0]	values[1]	valids[0x1]	517	1			T14	12		T15	9		T17	7
auto[0]	values[2]	valids[0x0]	533	1			T9	4		T15	11		T17	3
auto[0]	values[2]	valids[0x1]	281	1			T15	3		T17	3		T59	2
auto[0]	values[3]	valids[0x0]	554	1			T14	2		T15	2		T17	4
auto[0]	values[3]	valids[0x1]	257	1			T15	12		T17	4		T24	6
auto[0]	values[4]	valids[0x0]	476	1			T18	8		T15	5		T17	10
auto[0]	values[4]	valids[0x1]	308	1			T15	4		T17	6		T20	4
auto[0]	values[5]	valids[0x0]	527	1			T18	2		T15	7		T16	2
auto[0]	values[5]	valids[0x1]	296	1			T18	2		T15	2		T17	1
auto[0]	values[6]	valids[0x0]	509	1			T18	2		T15	9		T17	2
auto[0]	values[6]	valids[0x1]	270	1			T15	4		T131	4		T22	6
auto[0]	values[7]	valids[0x0]	528	1			T15	7		T17	5		T24	12
auto[0]	values[7]	valids[0x1]	300	1			T15	5		T16	2		T17	3
auto[0]	values[8]	valids[0x0]	3170	1			T9	6		T11	6		T18	4
auto[0]	values[8]	valids[0x1]	1850	1			T14	2		T15	25		T16	6
auto[1]	values[0]	valids[0x0]	4690	1			T3	114		T5	77		T6	64
auto[1]	values[0]	valids[0x1]	19395	1			T3	405		T5	164		T6	356
auto[1]	values[1]	valids[0x1]	668	1			T3	18		T5	11		T6	21
auto[1]	values[2]	valids[0x0]	444	1			T3	11		T5	14		T6	5
auto[1]	values[2]	valids[0x1]	304	1			T3	12		T5	5		T6	5
auto[1]	values[3]	valids[0x0]	425	1			T3	10		T10	3		T5	9
auto[1]	values[3]	valids[0x1]	306	1			T3	10		T10	4		T5	5
auto[1]	values[4]	valids[0x0]	495	1			T3	21		T5	7		T6	5
auto[1]	values[4]	valids[0x1]	316	1			T3	15		T5	4		T6	4
auto[1]	values[5]	valids[0x0]	439	1			T3	8		T10	9		T5	13
auto[1]	values[5]	valids[0x1]	258	1			T3	3		T5	3		T6	2
auto[1]	values[6]	valids[0x0]	390	1			T3	8		T5	14		T6	3
auto[1]	values[6]	valids[0x1]	278	1			T3	8		T5	2		T6	3
auto[1]	values[7]	valids[0x0]	442	1			T3	5		T5	5		T6	3
auto[1]	values[7]	valids[0x1]	273	1			T3	4		T5	4		T6	3
auto[1]	values[8]	valids[0x0]	2932	1			T3	61		T5	36		T6	37
auto[1]	values[8]	valids[0x1]	2033	1			T3	38		T5	28		T6	24