Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18602

1

T4

6

T3

230

T9

11

auto[1]

21231

1

T3

231

T5

61

T6

295

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14067

1

T4

6

T3

169

T9

11

auto[1]

25766

1

T3

292

T5

101

T6

327

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7507	1			T3	83		T9	3		T10	2
auto[524288:1048575]	4374	1			T3	78		T9	1		T19	2
auto[1048576:1572863]	3994	1			T4	1		T3	76		T10	2
auto[1572864:2097151]	4823	1			T3	22		T10	2		T11	1
auto[2097152:2621439]	4446	1			T3	30		T10	3		T11	1
auto[2621440:3145727]	4873	1			T4	5		T3	47		T9	4
auto[3145728:3670015]	4557	1			T3	43		T9	1		T10	3
auto[3670016:4194303]	5259	1			T3	82		T9	2		T10	2

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39230

1

T4

6

T3

440

T9

11

auto[1]

603

1

T3

21

T6

2

T15

8

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20636

1

T4

5

T3

216

T9

5

auto[1]

19197

1

T4

1

T3

245

T9

6

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1282	1			T3	14		T9	1		T10	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	689	1			T3	4		T5	4		T6	4
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	732	1			T3	12		T9	1		T5	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	396	1			T3	7		T5	1		T6	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	661	1			T3	11		T10	2		T5	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	342	1			T3	4		T5	2		T6	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	703	1			T3	3		T10	2		T11	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	373	1			T3	3		T5	7		T6	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	688	1			T3	3		T10	3		T11	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	371	1			T3	4		T5	1		T6	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	753	1			T4	5		T3	10		T9	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	424	1			T3	4		T5	2		T15	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	646	1			T3	5		T9	1		T19	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	374	1			T3	8		T6	4		T15	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	773	1			T3	3		T9	1		T11	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	466	1			T3	1		T5	10		T6	8
auto[0]	auto[1]	auto[0:524287]	auto[0]	828	1			T3	9		T9	2		T10	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	444	1			T3	5		T5	6		T6	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	721	1			T3	1		T19	2		T5	10
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	385	1			T5	9		T6	3		T15	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	643	1			T4	1		T3	12		T11	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	394	1			T3	11		T5	3		T6	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	670	1			T3	8		T19	1		T5	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	357	1			T3	2		T5	4		T6	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	673	1			T3	9		T5	9		T6	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	340	1			T3	7		T5	5		T6	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	746	1			T3	11		T9	3		T6	9
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	415	1			T3	5		T6	6		T15	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	744	1			T3	9		T10	3		T6	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	411	1			T3	7		T6	2		T15	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	730	1			T3	23		T9	1		T10	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	428	1			T3	15		T5	9		T6	7
auto[1]	auto[0]	auto[0:524287]	auto[0]	218	1			T3	2		T6	1		T15	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2225	1			T3	23		T6	10		T15	9
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	127	1			T3	3		T43	3		T45	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1144	1			T3	55		T43	44		T45	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	110	1			T3	2		T5	1		T6	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	710	1			T3	18		T5	1		T6	24
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	123	1			T3	1		T5	1		T6	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1364	1			T3	1		T5	2		T6	32
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	121	1			T3	1		T6	1		T15	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1131	1			T3	2		T6	5		T15	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	134	1			T3	1		T17	2		T20	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1021	1			T3	6		T17	26		T20	10
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	114	1			T3	1		T6	2		T43	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1125	1			T3	4		T6	23		T43	25
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	141	1			T5	5		T6	1		T15	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1155	1			T5	10		T6	7		T15	15
auto[1]	auto[1]	auto[0:524287]	auto[0]	151	1			T3	2		T5	1		T15	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	1670	1			T3	24		T5	1		T15	80
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	109	1			T5	6		T6	2		T15	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	760	1			T5	11		T6	9		T15	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	116	1			T3	2		T5	2		T17	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1018	1			T3	16		T5	3		T17	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	111	1			T3	1		T5	2		T6	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1122	1			T3	3		T5	3		T6	70
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	105	1			T3	1		T5	2		T15	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1017	1			T3	3		T5	2		T15	18
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	132	1			T3	1		T6	2		T17	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1248	1			T3	9		T6	42		T17	47
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	117	1			T3	2		T6	1		T17	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1026	1			T3	7		T6	5		T17	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	145	1			T3	6		T5	3		T6	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1421	1			T3	34		T5	5		T6	52

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	9583	1			T4	5		T3	92		T9	5
auto[0]	auto[0]	auto[1]	90	1			T3	4		T15	1		T43	2
auto[0]	auto[1]	auto[0]	8853	1			T4	1		T3	132		T9	6
auto[0]	auto[1]	auto[1]	76	1			T3	2		T15	1		T43	1
auto[1]	auto[0]	auto[0]	10730	1			T3	113		T5	20		T6	107
auto[1]	auto[0]	auto[1]	233	1			T3	7		T6	1		T15	2
auto[1]	auto[1]	auto[0]	10064	1			T3	103		T5	41		T6	186
auto[1]	auto[1]	auto[1]	204	1			T3	8		T6	1		T15	4