Group : spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg
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Group : spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv



Summary for Group spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_tx_size 8 0 8 100.00 100 1 1 0


Summary for Variable cp_tx_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_tx_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
specific_sizes[4] 24198 1 T32 1336 T47 12 T48 134
specific_sizes[2048] 1501 1 T8 104 T298 30 T299 2
specific_sizes[4092] 1096 1 T300 1 T301 62 T302 590
sizes[0] 629689 1 T3 268 T7 712 T32 1336
sizes[1] 433801 1 T183 90 T156 17754 T200 6
sizes[2] 173317 1 T8 104 T303 574 T49 16
sizes[3] 59751 1 T304 14664 T305 15535 T306 11442
sizes[4] 23196 1 T300 1 T301 62 T302 590

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%